blob: 98c0debef8fa9d67a2fb86a0e42d6e207ad89c09 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
|
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_GLYMUR_H
#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_GLYMUR_H
/* VIDEO_CC clocks */
#define VIDEO_CC_AHB_CLK 0
#define VIDEO_CC_AHB_CLK_SRC 1
#define VIDEO_CC_MVS0_CLK 2
#define VIDEO_CC_MVS0_CLK_SRC 3
#define VIDEO_CC_MVS0_DIV_CLK_SRC 4
#define VIDEO_CC_MVS0_FREERUN_CLK 5
#define VIDEO_CC_MVS0_SHIFT_CLK 6
#define VIDEO_CC_MVS0C_CLK 7
#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 8
#define VIDEO_CC_MVS0C_FREERUN_CLK 9
#define VIDEO_CC_MVS0C_SHIFT_CLK 10
#define VIDEO_CC_MVS1_CLK 11
#define VIDEO_CC_MVS1_DIV_CLK_SRC 12
#define VIDEO_CC_MVS1_FREERUN_CLK 13
#define VIDEO_CC_MVS1_SHIFT_CLK 14
#define VIDEO_CC_PLL0 15
#define VIDEO_CC_SLEEP_CLK 16
#define VIDEO_CC_SLEEP_CLK_SRC 17
#define VIDEO_CC_XO_CLK 18
#define VIDEO_CC_XO_CLK_SRC 19
/* VIDEO_CC power domains */
#define VIDEO_CC_MVS0_GDSC 0
#define VIDEO_CC_MVS0C_GDSC 1
#define VIDEO_CC_MVS1_GDSC 2
/* VIDEO_CC resets */
#define VIDEO_CC_INTERFACE_BCR 0
#define VIDEO_CC_MVS0_BCR 1
#define VIDEO_CC_MVS0C_BCR 2
#define VIDEO_CC_MVS0C_FREERUN_CLK_ARES 3
#define VIDEO_CC_MVS0_FREERUN_CLK_ARES 4
#define VIDEO_CC_MVS1_FREERUN_CLK_ARES 5
#define VIDEO_CC_XO_CLK_ARES 6
#define VIDEO_CC_MVS1_BCR 7
#endif
|
