1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "iris_core.h"
#include "iris_ctrls.h"
#include "iris_platform_common.h"
#include "iris_resources.h"
#include "iris_hfi_gen1.h"
#include "iris_hfi_gen1_defines.h"
#include "iris_vpu_buffer.h"
#include "iris_vpu_common.h"
#include "iris_instance.h"
#include "iris_platform_milos.h"
#include "iris_platform_sc7280.h"
#include "iris_platform_sm8250.h"
static const struct iris_firmware_desc iris_milos_desc = {
.firmware_data = &iris_hfi_milos_data,
.get_vpu_buffer_size = iris_vpu_buf_size,
.fwname = "qcom/vpu/vpu20_p2_gen2_s7.mbn",
};
static const struct iris_firmware_desc iris_vpu20_p1_gen1_desc = {
.firmware_data = &iris_hfi_gen1_data,
.get_vpu_buffer_size = iris_vpu_buf_size,
.fwname = "qcom/vpu/vpu20_p1.mbn",
};
static const struct iris_firmware_desc iris_vpu20_p1_gen2_s6_desc = {
.firmware_data = &iris_hfi_gen2_data,
.get_vpu_buffer_size = iris_vpu33_buf_size,
.fwname = "qcom/vpu/vpu20_p1_gen2_s6.mbn",
};
static const struct iris_firmware_desc iris_vpu20_p4_gen1_desc = {
.firmware_data = &iris_hfi_gen1_data,
.get_vpu_buffer_size = iris_vpu_buf_size,
.fwname = "qcom/vpu/vpu20_p4.mbn",
};
static const u32 iris_fmts_vpu2_dec[] = {
[IRIS_FMT_H264] = V4L2_PIX_FMT_H264,
[IRIS_FMT_HEVC] = V4L2_PIX_FMT_HEVC,
[IRIS_FMT_VP9] = V4L2_PIX_FMT_VP9,
};
static struct platform_inst_caps platform_inst_cap_vpu2 = {
.min_frame_width = 128,
.max_frame_width = 8192,
.min_frame_height = 128,
.max_frame_height = 8192,
.max_mbpf = 138240,
.mb_cycles_vsp = 25,
.mb_cycles_vpp = 200,
.max_frame_rate = MAXIMUM_FPS,
.max_operating_rate = MAXIMUM_FPS,
};
static const struct icc_info iris_icc_info_vpu2[] = {
{ "cpu-cfg", 1000, 1000 },
{ "video-mem", 1000, 15000000 },
};
static const char * const iris_clk_reset_table_vpu2[] = { "bus", "core" };
static const char * const iris_pmdomain_table_vpu2[] = { "venus", "vcodec0" };
static const struct tz_cp_config tz_cp_config_vpu2[] = {
{
.cp_start = 0,
.cp_size = 0x25800000,
.cp_nonpixel_start = 0x01000000,
.cp_nonpixel_size = 0x24800000,
},
};
const struct iris_platform_data milos_data = {
.firmware_desc_gen1 = &iris_milos_desc,
.vpu_ops = &iris_vpu2_ops,
.icc_tbl = iris_icc_info_milos,
.icc_tbl_size = ARRAY_SIZE(iris_icc_info_milos),
.bw_tbl_dec = sm8250_bw_table_dec,
.bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec),
.pmdomain_tbl = iris_pmdomain_table_vpu2,
.pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu2),
.opp_pd_tbl = milos_opp_pd_table,
.opp_pd_tbl_size = ARRAY_SIZE(milos_opp_pd_table),
.clk_tbl = sm8250_clk_table,
.clk_tbl_size = ARRAY_SIZE(sm8250_clk_table),
.opp_clk_tbl = sm8250_opp_clk_table,
.clk_rst_tbl = iris_clk_reset_table_vpu2,
.clk_rst_tbl_size = ARRAY_SIZE(iris_clk_reset_table_vpu2),
.dma_mask = 0xe0000000 - 1,
.inst_iris_fmts = iris_fmts_vpu2_dec,
.inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu2_dec),
.inst_caps = &platform_inst_cap_milos,
.tz_cp_config_data = tz_cp_config_vpu2,
.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu2),
.num_vpp_pipe = 2,
.max_session_count = 16,
.max_core_mbpf = ((4096 * 2176) / 256) * 2,
.max_core_mbps = ((3840 * 2176) / 256) * 30 + ((1920 * 1088) / 256) * 30,
};
const struct iris_platform_data sc7280_data = {
.firmware_desc_gen1 = &iris_vpu20_p1_gen1_desc,
.firmware_desc_gen2 = &iris_vpu20_p1_gen2_s6_desc,
.vpu_ops = &iris_vpu2_ops,
.icc_tbl = iris_icc_info_vpu2,
.icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2),
.bw_tbl_dec = sc7280_bw_table_dec,
.bw_tbl_dec_size = ARRAY_SIZE(sc7280_bw_table_dec),
.pmdomain_tbl = iris_pmdomain_table_vpu2,
.pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu2),
.opp_pd_tbl = sc7280_opp_pd_table,
.opp_pd_tbl_size = ARRAY_SIZE(sc7280_opp_pd_table),
.clk_tbl = sc7280_clk_table,
.clk_tbl_size = ARRAY_SIZE(sc7280_clk_table),
.opp_clk_tbl = sc7280_opp_clk_table,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.inst_iris_fmts = iris_fmts_vpu2_dec,
.inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu2_dec),
.inst_caps = &platform_inst_cap_vpu2,
.tz_cp_config_data = tz_cp_config_vpu2,
.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu2),
.num_vpp_pipe = 1,
.no_aon = true,
.max_session_count = 16,
.max_core_mbpf = 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256,
/* max spec for SC7280 is 4096x2176@60fps */
.max_core_mbps = 4096 * 2176 / 256 * 60,
};
const struct iris_platform_data sm8250_data = {
.firmware_desc_gen1 = &iris_vpu20_p4_gen1_desc,
.vpu_ops = &iris_vpu2_ops,
.icc_tbl = iris_icc_info_vpu2,
.icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2),
.clk_rst_tbl = iris_clk_reset_table_vpu2,
.clk_rst_tbl_size = ARRAY_SIZE(iris_clk_reset_table_vpu2),
.bw_tbl_dec = sm8250_bw_table_dec,
.bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec),
.pmdomain_tbl = iris_pmdomain_table_vpu2,
.pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu2),
.opp_pd_tbl = sm8250_opp_pd_table,
.opp_pd_tbl_size = ARRAY_SIZE(sm8250_opp_pd_table),
.clk_tbl = sm8250_clk_table,
.clk_tbl_size = ARRAY_SIZE(sm8250_clk_table),
.opp_clk_tbl = sm8250_opp_clk_table,
/* Upper bound of DMA address range */
.dma_mask = 0xe0000000 - 1,
.inst_iris_fmts = iris_fmts_vpu2_dec,
.inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu2_dec),
.inst_caps = &platform_inst_cap_vpu2,
.tz_cp_config_data = tz_cp_config_vpu2,
.tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu2),
.num_vpp_pipe = 4,
.max_session_count = 16,
.max_core_mbpf = NUM_MBS_8K,
.max_core_mbps = ((7680 * 4320) / 256) * 60,
};
|
