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8 daysMerge branches 'clk-pile' and 'clk-microchip' into clk-nextStephen Boyd
* clk-pile: (111 commits) clk: microchip: mpfs: fix regmap_update_bits() mask/val order clk: visconti: Make sure clk_init_data is fully initialized clk: ti: Make sure clk_init_data is fully initialized MAINTAINERS: Add Brian Masney and Jerome Brunet as co-maintainers for clk subsystem Drop Michael Turquette's clk maintainer entry clk: ti: composite: resolve parent clocks by DT index, not by name clk: ti: mux: resolve parent clocks by DT index, not by name clk: devres: fix cleanup in devm_clk_get_optional_enabled_with_rate() dt-bindings: clock: ti,keystone-gate: Convert to DT schema dt-bindings: clock: ti: Convert APLL clock to DT schema clk: zynq: pll: Fix kernel-doc after determine_rate() conversion dt-bindings: clock: ti,clockdomain: Convert to DT schema dt-bindings: clock: Correct white-space style clk: tegra: set up proper EMC clock implementation for Tegra114 clk: clocking-wizard: remove 20kHz restriction clk: clocking-wizard: optimize clock search clk: clocking-wizard: fix clock difference detection clk: mediatek: mt8135: Fix inverted gate control for devapc_ck clk: clocking-wizard: Program PLL CP/RES and lock parameters on reconfig clk: tegra: support 48MHz clock for pll_p_out1 ... * clk-microchip: clk: at91: Read "reg" with helper
8 daysMerge branches 'clk-imx', 'clk-rockchip', 'clk-samsung', 'clk-qcom' and ↵Stephen Boyd
'clk-allwinner' into clk-next * clk-imx: clk: imx95-blk-ctl: Fix REFCLK rise-fall mismatch on i.MX95 clk: imx95-blk-ctl: Add func_out_en clock for i.MX9x PCIe clk: imx: imx8qxp: add missing MODULE_DEVICE_TABLE() clk: imx: imx8qxp-lpcg: add missing MODULE_DEVICE_TABLE() clk: imx: Add audio PLL debugfs for K-divider control * clk-rockchip: clk: rockchip: rk3576: fix source muxes for SPI0..SPI4 clk: rockchip: Add clock controller for the RV1106 dt-bindings: clock: rockchip: Add RV1106 CRU support clk: rockchip: Fractional PLL coefficient on RK3588/RK3576 is two's complement clk: rockchip: Fix the fractional part denominator on RK3588/RK3576 PLLs clk: rockchip: rk3588: Allow VP2 the same sourcing options as other VPs clk: rockchip: rk3588: Don't change PLL rates when setting dclk_vop2_src * clk-samsung: clk: samsung: Don't include <linux/mod_devicetable.h> clk: samsung: pll: use kzalloc_flex clk: samsung: cpu: use kzalloc_flex clk: samsung: use kzalloc_flex clk: samsung: exynos990: Fix PERIS gate clock parents clk: samsung: exynos990: Add PERIS TMU_SUB_PCLK gate dt-bindings: clock: exynos990: Add CLK_GOUT_PERIS_TMU_SUB_PCLK * clk-qcom: (94 commits) clk: qcom: Add support for Qualcomm GPU Clock Controller on Shikra clk: qcom: Return expected ENOMEM error on dynamic allocation failure clk: qcom: apss-ipq-pll: Add IPQ5210 support dt-bindings: clock: qcom,a53pll: Add IPQ5210 compatible clk: qcom: Add support for videocc driver on Qualcomm Maili SoC dt-bindings: clock: qcom: Add Qualcomm Maili video clock controller dt-bindings: clock: qcom: Add Qualcomm Shikra GPU clock controller dt-bindings: clock: qcom: Add Qualcomm Shikra Display clock controller clk: qcom: gpucc-qcm2290: Park RCG's clk source at XO during disable clk: qcom: gpucc-qcm2290: Keep the critical clocks always-on from probe clk: qcom: gpucc-qcm2290: Move to the latest common qcom_cc_probe() model clk: qcom: gpucc-qcm2290: Drop pm_clk handling clk: qcom: qcm2290: Update DISPCC and GPUCC GDSC *wait_val values clk: qcom: qcm2290: Add RETAIN_FF_ENABLE flag for DISPCC and GPUCC GDSCs clk: qcom: qcm2290: Set POLL_CFG_GDSCR flag for DISPCC and GPUCC GDSCs clk: qcom: dispcc-qcm2290: Enable runtime PM support clk: qcom: dispcc-qcm2290: Move to the latest common qcom_cc_probe() model clk: qcom: gcc-qcm2290: Keep the critical clocks always-on from probe dt-bindings: clock: qcom,qcm2290-dispcc: Add missing power-domains property clk: qcom: Add Audio Core clock controller support on Qualcomm Shikra SoC ... * clk-allwinner: clk: sunxi-ng: sun6i-rtc: add a733 support clk: sunxi-ng: sun6i-rtc: split main oscillator div and gate clk: sunxi-ng: div: add read-only operation support clk: sunxi-ng: mux: fix determine helper rate propagation clk: sunxi-ng: mux: remove unneeded export clk: sunxi-ng: sun6i-rtc: Add feature bit for IOSC calibration clk: sunxi-ng: sun6i-rtc: clean up DT usage clk: sunxi-ng: fix ccu probe clock unregister on error dt-bindings: rtc: sun6i: add sun60i-a733 support dt-bindings: rtc: sun6i: no clock-output-names on h616/r329
8 daysMerge branches 'clk-renesas', 'clk-thead', 'clk-mobileye', 'clk-amlogic' and ↵Stephen Boyd
'clk-spacemit' into clk-next * clk-renesas: clk: renesas: Add R-Car X5H CPG driver dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse Generator clk: r9a08g045: Add clocks and resets for CAN-FD dt-bindings: clock: renesas,versaclock7: Update maintainer clk: renesas: r9a09g047: Add LVDS clocks and resets clk: renesas: r9a09g077: Add LCDC and PLL3 clock support for RZ/T2H display pipeline clk: renesas: rzv2h-cpg: Extract PLL calculation helpers into shared library clk: renesas: rzv2h-cpg: Use per-SoC PLL reference frequency for calculations clk: renesas: r9a08g046: Add USB2.0 clock and reset entries clk: renesas: r9a09g077: Add RTC clocks clk: renesas: cpg-mssr: Implement dedicated MSTP delay logic for RZ/T2H LCDC and RTC clk: renesas: r9a08g046: Add clock and reset entries for GE3D clk: renesas: r9a08g046: Add clock and reset entries for SDHI clk: renesas: r9a09g047: Add audio clock and reset support dt-bindings: clock: renesas: Add audio clock inputs for RZ/V2H family dt-bindings: clock: renesas,r9a09g077/87: Add PCLKRTC clock ID dt-bindings: clock: renesas,r9a09g077/87: Add LCDC_CLKD clock ID * clk-thead: clk: thead: allow COMPILE_TEST builds * clk-mobileye: clk: eyeq: Add EyeQ7H compatibles clk: eyeq: Drop PLL, dividers, and fixed factors structs clk: eyeq: Convert clocks declaration to eqc_clock clk: eyeq: Introduce a generic clock type clk: eyeq: Prefix the PLL registers with the PLL type clk: fixed-factor: Export __clk_hw_register_fixed_factor() clk: fixed-factor: Rework initialization with parent clocks reset: eyeq: Add EyeQ7H compatibles dt-bindings: soc: mobileye: Add EyeQ7H OLB * clk-amlogic: clk: amlogic: Add A9 peripherals clock controller driver dt-bindings: clock: Add Amlogic A9 peripherals clock controller clk: amlogic: Add A9 AO clock controller driver dt-bindings: clock: Add Amlogic A9 AO clock controller clk: meson: align gxbb_32k_clk_sel number of parents with actual count * clk-spacemit: clk: spacemit: k3: fix missing /2 factor in i2s sysclk dividers clk: spacemit: k3: fix i2s clock topology dt-bindings: soc: spacemit: k3: add i2s_sysclk, i2s_bclk_factor and i2s1_sysclk_src IDs clk: spacemit: k3: Add UFS refclk clock dt-bindings: soc: spacemit: k3: Add clock ID for UFS refclk clk: spacemit: k3: fix parent clock of UFS aclk
12 daysMerge tag 'clk-misc-round-two-for-v7.3' of ssh://github.com/masneyb/linux ↵Stephen Boyd
into clk-pile Pull clk patches from Brian Masney: - New clock controller drivers for the Cix Sky1 audio subsystem (AUDSS), UltraRISC DP1000, and MediaTek MT8173 MFG_TOP, along with their devicetree bindings. Si549 support was added to the existing si544 driver. - New clock and reset support for the Aspeed AST2700 PECI controller and Airoha EN7523 PCIe PERSTOUT reset lines. - The clk core gains devm_clk_bulk_get_enable() as the mandatory counterpart to the existing optional variant, and exports devm_clk_hw_register_composite_pdata() for modular drivers. - Tegra gets a proper EMC clock implementation for Tegra114, 48MHz pll_p_out1 support needed for UEFI on Surface2, and the Xilinx clocking-wizard gains PLL charge pump/lock parameter programming during dynamic reconfiguration. - Bug fixes for a NULL pointer dereference from uninitialized clk_init_data in the eswin driver, an IO remap leak in the MediaTek pllfh error path, inverted gate control for MT8135 devapc_ck, a missing OF node put in tegra124-emc on registration failure, a prepare reference leak in the palmas driver, unregistered PLLs on MT6735 probe failure, a missing kasprintf NULL check in pmc_atom, PCIe warm boot instability in the Airoha EN7523 driver, and a clocking-wizard clock difference detection bug. - Various cleanups across tegra, st, and mvebu providers to stop misusing the consumer clock API, along with other minor fixes and improvements. Signed-off-by: Brian Masney <bmasney@redhat.com> * tag 'clk-misc-round-two-for-v7.3' of ssh://github.com/masneyb/linux: (45 commits) clk: tegra: set up proper EMC clock implementation for Tegra114 clk: clocking-wizard: remove 20kHz restriction clk: clocking-wizard: optimize clock search clk: clocking-wizard: fix clock difference detection clk: mediatek: mt8135: Fix inverted gate control for devapc_ck clk: clocking-wizard: Program PLL CP/RES and lock parameters on reconfig clk: tegra: support 48MHz clock for pll_p_out1 clk: aspeed: add AST2700 PECI clock dt-bindings: clock: ast2700: add PECI clock clk: mediatek: Add mt8173-mfgtop driver dt-bindings: clock: mediatek: Add mt8173 mfgtop clk: tegra: clean-up simple provider misuse of the consumer API clk: st: clean-up simple provider misuse of the consumer API clk: mvebu: clean-up simple provider misuse of the consumer API clk: remove conditional return with no effect clk: Add devm_clk_bulk_get_enable() clk: en7523: add support for dedicated PCIe PERSTOUT reset dt-bindings: clock: airoha: Add additional reset for PCIe PERSTOUT arm64: dts: cix: sky1: add audss cru reset: cix: add sky1 audss auxiliary reset driver ...
2026-08-05dt-bindings: clock: rockchip: Add RV1106 CRU supportSimon Glass
Add the clock binding header and schema for the Rockchip RV1106 clock and reset unit. The clock IDs are numbered continuously from 0, in the same way as the RV1103B. The header also covers the MMC drive and sample phase clocks, which the CRU provides using control registers in the GRF region. The RV1103 is a package variant of the RV1106 and uses the same CRU. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260729133609.3465563-2-sjg@chromium.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2026-08-05Merge tag 'renesas-r8a78000-dt-binding-defs-tag2' into renesas-clk-for-v7.3Geert Uytterhoeven
Renesas R-Car X5H CPG DT Binding Definitions DT bindings and binding definitions for the Renesas R-Car X5H (R8A78000) Clock Pulse Generator (CPG), shared by driver and DT source files.
2026-08-05dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse GeneratorGeert Uytterhoeven
Document support for the Renesas R-Car X5H Clock Pulse Generator, and add binding definitions for a limited initial set of clocks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Tested-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/7a33c99816c850faeec5c17532811faf78959a1d.1785941595.git.geert+renesas@glider.be
2026-07-30dt-bindings: clock: qcom: Add Qualcomm Maili video clock controllerJagadeesh Kona
Add device tree bindings for the video clock controller on Qualcomm Maili SoC. Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260717-maili_videocc-v3-1-6656694b06a7@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-30dt-bindings: clock: qcom: Add Qualcomm Shikra AudioCoreCC and AudioCoreCSRImran Shaik
Add device tree bindings for the Audio Core Clock Controller (AudioCoreCC) that provides clocks and Audio Core CSR that provides resets on Qualcomm Shikra SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260724-shikra-audiocorecc-v4-1-0a89bb13d817@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-30dt-bindings: clock: qcom: Document Nord GPU clock controllersTaniya Das
Add Device Tree binding documentation for the GPU clock controllers on the Qualcomm Nord platform. The platform includes two GPU clock controller instances, GPUCC and GPU2CC. Document the compatible strings for both controllers. Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260724-nords_mm_v1-v3-5-32b45232217f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-30dt-bindings: clock: qcom: Document Nord display clock controllerTaniya Das
Add Device Tree binding documentation for the display clock controller on the Qualcomm Nord SoC. The Nord platform contains two instances of the display clock controller, DISPCC_0 and DISPCC_1. Update the bindings to include compatible strings for both instances. Reviewed-by: Alexandre Mergnat <amergnat@baylibre.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260724-nords_mm_v1-v3-3-32b45232217f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-30dt-bindings: clock: qcom: Add Maili global clock controllerTaniya Das
Add device tree bindings for the global clock controller (GCC) on the Qualcomm Maili SoC by extending the existing Qualcomm Hawi GCC bindings, since the Maili GCC is identical to the Hawi GCC apart from a few additional clocks. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260730-maili_initial_clock-v4-3-ed52ade264f0@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-30dt-bindings: clock: qcom: gcc-mdm9607: Drop SYSTEM_NOC_BFDCD_CLK_SRCStephan Gerhold
This clock does not exist in the hardware, it has no consumers and reading/writing to the registers fails. Drop it from the bindings. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20260706-qcom-clk-mdm9607-fixes-v2-9-745565101869@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-29dt-bindings: soc: spacemit: k3: add i2s_sysclk, i2s_bclk_factor and ↵Troy Mitchell
i2s1_sysclk_src IDs Add three new clock IDs to expose clocks introduced by the topology fix: - CLK_MPMU_I2S_SYSCLK (51): the common i2s sysclk DDN at MPMU_ISCCR1 - CLK_MPMU_I2S_BCLK_FACTOR (52): the implicit /2 factor feeding i2s_bclk - CLK_MPMU_I2S1_SYSCLK_SRC (53): the dedicated i2s1 sysclk source mux CLK_MPMU_I2S1_SYSCLK keeps its existing ID (34) but will be repointed to the real per-instance i2s1 clock in a subsequent patch. No in-tree user references this ID so the semantic change is contained. Fixes: efe897b557e2 ("dt-bindings: soc: spacemit: k3: add clock support") Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260717-k3-clk-fix-i2s-v1-1-e95001a692ee@linux.spacemit.com Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-07-28dt-bindings: clock: ast2700: add PECI clockRyan Chen
Add SCU1_CLK_PECI for the SoC1 PECI controller clock source, and SCU1_CLK_HPLL_DIV4 which serves as one of the PECI clock mux parents. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Brian Masney <bmasney@redhat.com>
2026-07-28dt-bindings: clock: mediatek: Add mt8173 mfgtopChen-Yu Tsai
The MFG (GPU) block on the MT8173 has a small glue layer, named MFG_TOP in the datasheet, that contains clock gates, some power sequence signal delays, and other unknown registers that get toggled when the GPU is powered on. The clock gates are exposed as clocks provided by a clock controller, while the power sequencing bits are exposed as one singular power domain. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Chen-Yu Tsai <wenst@chromium.org> Signed-off-by: Brian Masney <bmasney@redhat.com>
2026-07-28dt-bindings: soc: cix: add sky1 audss cru controllerJoakim Zhang
The Cix Sky1 Audio Subsystem (AUDSS) Clock and Reset Unit (CRU) groups clock muxing, gating and block-level software reset control in a single register block. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Joakim Zhang <joakim.zhang@cixtech.com> Signed-off-by: Brian Masney <bmasney@redhat.com>
2026-07-28dt-bindings: clock: ultrarisc: Add DP1000 Clock ControllerJia Wang
Add doc for the clock controller on the UltraRISC DP1000 RISC-V SoC. Signed-off-by: Jia Wang <wangjia@ultrarisc.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Brian Masney <bmasney@redhat.com>
2026-07-24dt-bindings: clock: Add Amlogic A9 peripherals clock controllerJian Hu
Add the peripherals clock controller dt-bindings for the Amlogic A9 SoC family. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Jian Hu <jian.hu@amlogic.com> Link: https://patch.msgid.link/20260701-a9_peripherals-v6-1-9630f39879e5@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2026-07-17dt-bindings: soc: mobileye: Add EyeQ7H OLBBenoît Monin
The Other Logic Blocks (OLB) found in Mobileye SoCs contain hardware sub-functions grouped in a logical device. The EyeQ7H features 14 such OLB. The main differences with the previous generation of SoC are that some blocks have two clock sources instead of one and that the clock source can be the one of the clock output of another OLB instead of the main oscillator. For the blocks with a single parent clock, the name of that clock is "ref", similar to what is done for the OLB of the previous SoC. The blocks with two parent clocks use either "ref" for the main oscillator, "ref_100p0" for a 100MHz reference clock or "ref_106p6" for 106.6MHz reference clock. Some OLB also contain a reset controller with one or more reset domain, like the blocks found in the EyeQ6H. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
2026-07-13dt-bindings: clock: exynos990: Add CLK_GOUT_PERIS_TMU_SUB_PCLKDenzeel Oliva
Add the missing TMU_SUB_PCLK clock ID for the Exynos990 PERIS CMU. Signed-off-by: Denzeel Oliva <wachiturroxd150@gmail.com> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://patch.msgid.link/20260613-exynos990-peris-fix-v3-v3-1-2b230db78ae4@gmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-07-11Merge branch ↵Bjorn Andersson
'20260707-b4-ipq9650_refgen_clocks-v1-1-e070624d03d2@oss.qualcomm.com' into clk-for-7.3 Merge the IPQ9650 refgen clock ids through a topic branch, in case they need to be referenced from DeviceTree branches as well before next release.
2026-07-11dt-bindings: clock: qcom: Add IPQ9650 REFGEN clock IDsKathiravan Thirumoorthy
Add the REFGEN clock IDs for the IPQ9650 SoC. These clocks are used to enable the REFGEN block, which provides the reference current to the PHYs in the SoC. Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260707-b4-ipq9650_refgen_clocks-v1-1-e070624d03d2@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-11Merge branch '20260624-glymur_camcc-v5-1-a321df74b1a1@oss.qualcomm.com' into ↵Bjorn Andersson
clk-for-7.3 Merge Glymur camera clock controller binding through topic branch, to allow sharing constants with DeviceTree branches.
2026-07-11dt-bindings: clock: qcom: Add Glymur camera clock controllerJagadeesh Kona
Add device tree bindings for the camera clock controller on Qualcomm Glymur SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260624-glymur_camcc-v5-1-a321df74b1a1@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-10dt-bindings: soc: spacemit: k3: Add clock ID for UFS refclkYixun Lan
Add clock ID for the UFS refclk clock in SpacemiT K3 SoC. Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260630-06-clk-ufs-support-v1-2-cf7521d1d0fe@kernel.org Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-07-07Merge branch ↵Bjorn Andersson
'20260608-shikra-gcc-rpmcc-clks-v5-2-94cefe092ee3@oss.qualcomm.com' into clk-for-7.3 Merge Shikra RPM and global clock controller bindings through topic branch, to allow constants to be made available to DeviceTree branches as well.
2026-07-07dt-bindings: clock: qcom: Add Qualcomm Shikra SoC Global Clock ControllerImran Shaik
Add device tree bindings for the global clock controller on Qualcomm Shikra SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260608-shikra-gcc-rpmcc-clks-v5-2-94cefe092ee3@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06dt-bindings: clock: qcom: Add Hawi video clock controllerLin Li
Add device tree bindings for the video clock controller on Qualcomm Hawi SoC. Signed-off-by: Lin Li <zhuolin.li@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260702-hawi-videocc-v1-1-6c1e640b0954@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06dt-bindings: clock: qcom: Add EVA clock and reset controller for Glymur SoCTaniya Das
Add the device tree bindings for the enhanced video analytics(EVA) clock controller which is required on Qualcomm Glymur SoC. The controller provides clocks, resets and power domains for the EVA subsystem. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260617-evacc_glymur-v2-2-905108dacaaa@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-07-06dt-bindings: rtc: sun6i: add sun60i-a733 supportJerome Brunet
Add a new rtc compatible for the sun60i-a733 SoC and new IDs for the peripheral oscillator clock gates of this SoC. Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://patch.msgid.link/20260706-a733-rtc-v4-2-f330728db3d3@baylibre.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2026-06-30Merge tag 'renesas-r9a09g077-dt-binding-defs-tag7' into renesas-clk-for-v7.3Geert Uytterhoeven
Renesas RZ/T2H and RZ/N2H LCDC and RTC Clock DT Binding Definitions LCD Controller and Real-Time Clock DT binding definitions for the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs, shared by driver and DT source files.
2026-06-29dt-bindings: clock: Add ESWIN eic7700 HSP clock and reset generatorXuyang Dong
Add bindings for the high-speed peripherals clock and reset generator on the ESWIN EIC7700 HSP. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Xuyang Dong <dongxuyang@eswincomputing.com> Signed-off-by: Brian Masney <bmasney@redhat.com>
2026-06-29dt-bindings: clock: Add spread spectrum definitionPeng Fan
Per dt-schema, the modulation methods are: down-spread(3), up-spread(2), center-spread(1), no-spread(0). So define them in dt-bindings to avoid write the magic number in device tree. Reviewed-by: Brian Masney <bmasney@redhat.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Sebin Francis <sebin.francis@ti.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Brian Masney <bmasney@redhat.com>
2026-06-29dt-bindings: clock: Add Amlogic A9 AO clock controllerJian Hu
Add the Always-On clock controller dt-bindings for the Amlogic A9 SoC family. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Jian Hu <jian.hu@amlogic.com> Link: https://patch.msgid.link/20260623-a9_aoclk-v5-1-c7cb1ff9ebf1@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2026-06-25Merge branches 'clk-microchip' and 'clk-qcom' into clk-nextStephen Boyd
* clk-microchip: clk: at91: keep securam node alive while mapping it clk: at91: sama7d65: add peripheral clock for I3C clk: microchip: mpfs-ccc: fix peripheral driver registration failures after oob fix clk: at91: sam9x7: Fix gmac_gclk clock definition clk: at91: sam9x7: Rename macb0_clk to gmac_clk clk: at91: sam9x7: Remove gmac peripheral clock with ID 67 clk: microchip: rename clk-core to clk-pic32 * clk-qcom: (32 commits) clk: qcom: regmap-phy-mux: Rework the implementation clk: qcom: a53: Corrected frequency multiplier for 1152MHz clk: qcom: camcc-milos: Declare icc path dependency for CAMSS_TOP_GDSC clk: qcom: gdsc: Support enabling interconnect path for power domain dt-bindings: clock: qcom,milos-camcc: Document interconnect path interconnect: Add devm_of_icc_get_by_index() as exported API for users clk: qcom: camcc-x1p42100: Add support for camera clock controller clk: qcom: camcc-x1e80100: Add support for camera QDSS debug clocks clk: qcom: videocc-x1p42100: Add support for video clock controller dt-bindings: clock: qcom: Add X1P42100 camera clock controller dt-bindings: clock: qcom: Add X1P42100 video clock controller clk: qcom: nord: negcc: add support for the USB2 PHY reset dt-bindings: clock: qcom: add the definition for the USB2 PHY reset clk: qcom: clk-rpmh: Make all VRMs optional clk: qcom: Add support for global clock controller on Hawi clk: qcom: clk-alpha-pll: Add support for Taycan EHA_T PLL clk: qcom: Add Hawi TCSR clock controller driver clk: qcom: rpmh: Add support for Hawi RPMH clocks dt-bindings: clock: qcom: Add Hawi global clock controller dt-bindings: clock: qcom: Add Hawi TCSR clock controller ...
2026-06-25Merge branches 'clk-ti', 'clk-samsung', 'clk-rockchip' and 'clk-spacemit' ↵Stephen Boyd
into clk-next * clk-ti: clk: keystone: sci-clk: fix application of sizeof to pointer clk: keystone: don't cache clock rate * clk-samsung: clk: samsung: exynos990: Fix PERIC0/1 USI clock types clk: samsung: exynos850: mark APM I3C clocks as critical * clk-rockchip: clk: rockchip: allow COMPILE_TEST builds clk: rockchip: rk3588: add GATE_GRF clocks for I2S MCLK output to IO soc: rockchip: rk3588: add SYS_GRF SOC_CON6 register offset clk: rockchip: add helper to register auxiliary GRFs clk: rockchip: allow grf_type_sys lookup in aux_grf_table dt-bindings: clock: rockchip,rk3588-cru: add I2S MCLK output to IO clock IDs * clk-spacemit: clk: spacemit: k3: Add PCIe DBI clock dt-bindings: soc: spacemit: k3: Add PCIe DBI clock IDs clk: spacemit: k3: Fix PCIe clock register offset clk: spacemit: k3: Switch to pll2_d6 as parent for PCIe clock
2026-06-25Merge branches 'clk-renesas', 'clk-socfpga', 'clk-amlogic' and 'clk-canaan' ↵Stephen Boyd
into clk-next * clk-renesas: (36 commits) clk: renesas: r9a08g045: Drop unused pm_domain header file clk: renesas: r8a779g0: Add DSC clock clk: renesas: rzg2l: Rename iterator in for_each_mod_clock() to avoid shadowing clk: renesas: r9a08g045: Drop unused DEF_G3S_MUX macro clk: renesas: rzg2l: Rename RZG3L-prefixed PLL macros to CPG-prefixed ones clk: renesas: rzg3s/rzg3l: Simplify PLL configuration macro clk: renesas: rzg2l: Simplify SAM PLL configuration macro clk: renesas: r8a73a4: Add ZT/ZTR trace clocks dt-bindings: clock: renesas,cpg-clocks: Document ZT/ZTR trace clock on R-Mobile APE6 clk: renesas: r9a08g046: Add RSPI clocks and resets clk: renesas: r9a08g046: Add SSIF-2 clocks and resets clk: renesas: r9a08g046: Add RSCI clocks and resets clk: renesas: cpg-mssr: Add number of clock cells check clk: renesas: rzg2l: Refactor rzg3l_cpg_pll_clk_endisable() clk: renesas: rzg2l: Consolidate DEF_MUX() and DEF_MUX_FLAGS() clk: renesas: r9a08g046: Add IA55_PCLK to critical module clocks clk: renesas: r9a09g047: Add support for LCDC{0,1} clocks and resets clk: renesas: r9a09g047: Add support for DSI clocks and resets clk: renesas: r9a09g047: Add support for SMUX2_DSI{0,1}_CLK clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_CSDIV clocks ... * clk-socfpga: clk: socfpga: agilex: implement l3_main_free_clk * clk-amlogic: dt-bindings: clock: amlogic: t7: Add missing mpll3 parent clock dt-bindings: clock: amlogic: Fix redundant hyphen in "amlogic,t7-gp1--pll" string. * clk-canaan: clk: canaan: Add clock driver for Canaan K230 dt-bindings: clock: Add Canaan K230 clock controller
2026-06-22dt-bindings: clock: renesas,r9a09g077/87: Add PCLKRTC clock IDLad Prabhakar
Add the peripheral clock ID definition for the Real-Time Clock (PCLKRTC) on the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. Note that the PCLKRTC clock is utilized as the operating clock source for the RTC IP. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260615143943.1610095-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-06-22dt-bindings: clock: renesas,r9a09g077/87: Add LCDC_CLKD clock IDLad Prabhakar
Add the LCDC clockd (LCDC_CLKD) definition for the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. LCDC_CLKD is used as the operating clock for LCDC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260615104845.4122868-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-06-06dt-bindings: clock: qcom: Add X1P42100 camera clock controllerJagadeesh Kona
Add X1P42100 camera clock controller support and clock bindings for camera QDSS debug clocks which are applicable for both X1E80100 and X1P42100 platforms. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260507-purwa-videocc-camcc-v5-2-fc3af4130282@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-06-06dt-bindings: clock: qcom: Add X1P42100 video clock controllerJagadeesh Kona
Add device tree bindings for the video clock controller on Qualcomm X1P42100 (Purwa) SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260507-purwa-videocc-camcc-v5-1-fc3af4130282@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-06-02dt-bindings: soc: spacemit: k3: Add PCIe DBI clock IDsYixun Lan
Add clock IDs of PCIe DBI (Data Bus Interface) clock. Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260511-06-pci-clk-fix-v2-3-c9a5e563bab3@kernel.org Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-05-21dt-bindings: clock: qcom: add the definition for the USB2 PHY resetBartosz Golaszewski
Provide the USB2 PHY reset definition in dt-bindings for the Nord negcc module in order to enable adding the USB nodes in DTS. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260518-nord-clk-usb2-phy-v2-1-17a86cb307c3@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-21dt-bindings: clock: Add Canaan K230 clock controllerXukai Wang
This patch adds the Device Tree binding for the clock controller on Canaan k230. The binding defines the clocks and the required properties to configure them correctly. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Xukai Wang <kingxukai@zohomail.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2026-05-15dt-bindings: clock: renesas,cpg-clocks: Document ZT/ZTR trace clock on ↵Marek Vasut
R-Mobile APE6 Document the ZT trace bus and ZTR trace clocks on R-Mobile APE6. These clocks supply the coresight tracing modules, PTM, TPIU, ETB and replicator. Without these clocks, coresight tracing can not be operated. While this does change the ABI, it does so by extending the existing clock-output-names, therefore if old software is used with new DT, the coresight tracing parts will likely fail to probe, otherwise if new software is used with an old DT, there is no impact. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260502185557.93061-2-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2026-05-13dt-bindings: clock: qcom: Add Hawi global clock controllerVivek Aknurwar
Add device tree bindings for the global clock controller on the Qualcomm Hawi SoC. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Mike Tipton <mike.tipton@oss.qualcomm.com> Signed-off-by: Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260506-clk-hawi-v3-3-530b538679f1@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-13dt-bindings: clock: qcom: Add Hawi TCSR clock controllerVivek Aknurwar
Add bindings documentation for TCSR clock controller on the Qualcomm Hawi SoC. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Mike Tipton <mike.tipton@oss.qualcomm.com> Signed-off-by: Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260506-clk-hawi-v3-2-530b538679f1@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-13dt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for HawiVivek Aknurwar
Update documentation for the RPMH clock controller on the Qualcomm Hawi SoC. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Mike Tipton <mike.tipton@oss.qualcomm.com> Signed-off-by: Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260506-clk-hawi-v3-1-530b538679f1@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-05-12Merge branch ↵Bjorn Andersson
'20260106-qcom_ipq5332_cmnpll-v2-2-f9f7e4efbd79@oss.qualcomm.com' into clk-for-7.2 Merge the introduction of qcom,ipq5332-cmn-pll DeviceTree binding through a topic branch, to make it available to DeviceTree source tree as well.
generated by cgit v1.2.3 (git 2.25.1) at 2026-08-29 09:16:43 +0000