summaryrefslogtreecommitdiff
path: root/drivers/edac
AgeCommit message (Collapse)Author
3 daysMerge tag 'edac_updates_for_v7.3_rc2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras Pull forgotten EDAC updates from Borislav Petkov: "Somewhat belated (and forgotten :-\) EDAC updates lineup for v7.3: - Mark the mpc85xx and ThunderX EDAC drivers as orphaned due to lack of access to hardware - Remove the unused fake error injection interface from the EDAC debugfs code due to potential races between logging a fake and a real hw error - edac_mc_sysfs: Use sysfs_emit_at() for proper bounds checking - Remove Mark Gross from maintainer entries and move him to CREDITS - Load the AMD address translation library only on systems which can actually make use of it (have ECC memory) instead of on every AMD Zen system out there - In edac_altera, detect the SoC variant using the ECC manager's compatible string instead of the build architecture to select the correct interrupt layout, and remove leftover architecture-specific ifdeffery from the double-bit error handling path - Add a new reviewer for the Xilinx EDAC drivers - Unify address translation logic in Intel client EDAC drivers igen6 and ie31200 along with detecting memory controller counts at boot time instead of relying on hardcoded, platform specific numbers. Also, fix a bunch of issues in them; work by Qiuxu Zhuo - Add support for a new Intel processor platform Starfire which is a derivative of Panther Lake SoCs - The usual cleanups and fixlets all over" * tag 'edac_updates_for_v7.3_rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras: (24 commits) EDAC/thunderx: Orphan it EDAC/device_sysfs: Cleanup around edac_device_ctl_poll_msec_store() EDAC/device_sysfs: Use kstrtouint() for poll_msec to prevent truncation EDAC/igen6: Add Intel Starfire SoCs support EDAC/igen6: Refactor address translation logic EDAC/igen6: Remove redundant resource configuration tables EDAC/igen6: Detect present memory controllers at runtime EDAC/igen6: Simplify compute die ID comments EDAC/igen6: Remove unnecessary XOR on the zero-valued interleave bit EDAC/igen6: Fix Raptor Lake-P logged error address EDAC/igen6: Fix channel address decode for non-hash mode EDAC/igen6: Fix channel selection hash EDAC/igen6: Fix interleave boundary condition EDAC/ie31200: Decouple DIMM width decoding from enum order RAS/AMD/ATL: Remove conditional return with no effect EDAC: Remove redundant dev_err() MAINTAINERS: Add Radhey Shyam Pandey as Xilinx EDAC reviewer EDAC/altera: Remove remaining CONFIG_64BIT ifdefs in the DB-error path EDAC/altera: Use ECC manager compatible to select A10/S10 IRQ layout RAS/AMD/ATL, EDAC/amd64: Only load ATL when needed ...
4 daysMerge remote-tracking branches 'ras/edac-misc', 'ras/edac-drivers' and ↵Borislav Petkov (AMD)
'ras/edac-amd-atl' into edac-updates * ras/edac-misc: EDAC/thunderx: Orphan it EDAC/device_sysfs: Cleanup around edac_device_ctl_poll_msec_store() EDAC/device_sysfs: Use kstrtouint() for poll_msec to prevent truncation MAINTAINERS: Add Radhey Shyam Pandey as Xilinx EDAC reviewer MAINTAINERS: Remove Mark Gross from relevant entries EDAC/sysfs: Use sysfs_emit_at() in dimmdev_location_show() EDAC/mpc85xx: Orphan it * ras/edac-drivers: EDAC/igen6: Add Intel Starfire SoCs support EDAC/igen6: Refactor address translation logic EDAC/igen6: Remove redundant resource configuration tables EDAC/igen6: Detect present memory controllers at runtime EDAC/igen6: Simplify compute die ID comments EDAC/igen6: Remove unnecessary XOR on the zero-valued interleave bit EDAC/igen6: Fix Raptor Lake-P logged error address EDAC/igen6: Fix channel address decode for non-hash mode EDAC/igen6: Fix channel selection hash EDAC/igen6: Fix interleave boundary condition EDAC/ie31200: Decouple DIMM width decoding from enum order EDAC: Remove redundant dev_err() EDAC/altera: Remove remaining CONFIG_64BIT ifdefs in the DB-error path EDAC/altera: Use ECC manager compatible to select A10/S10 IRQ layout * ras/edac-amd-atl: RAS/AMD/ATL: Remove conditional return with no effect RAS/AMD/ATL, EDAC/amd64: Only load ATL when needed EDAC/debugfs: Remove the fake_inject debugfs interface Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
2026-08-18Merge tag 'x86-msr-2026-08-17' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 MSR updates from Ingo Molnar: - Streamline the x86 MSR handling APIs along the 64-bit variants, simplifying the interfaces. Removal of the old APIs is planned for the next cycle, to reduce churn & integration pain (Juergen Gross) * tag 'x86-msr-2026-08-17' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (21 commits) x86/mce: Work around build warning after MSR-interface switch cpufreq: Stop using 32-bit MSR interfaces x86/featctl: Stop using 32-bit MSR interfaces KVM/x86: Stop using 32-bit MSR interfaces x86/mtrr: Stop using 32-bit MSR interfaces acpi: Stop using 32-bit MSR interfaces powercap: Stop using 32-bit MSR interfaces thermal/intel: Stop using 32-bit MSR interfaces x86/olpc: Stop using 32-bit MSR interfaces x86/hyperv: Stop using 32-bit MSR interfaces hwmon: Stop using 32-bit MSR interfaces EDAC: Stop using 32-bit MSR interfaces x86/cpu: Stop using 32-bit MSR interfaces x86/apic: Stop using 32-bit MSR interfaces x86/resctrl: Stop using 32-bit MSR interfaces x86/tsc: Stop using 32-bit MSR interfaces x86/amd: Stop using 32-bit MSR interfaces x86/pci: Stop using 32-bit MSR interfaces x86/hygon: Stop using 32-bit MSR interfaces x86/mce: Stop using 32-bit MSR interfaces ...
2026-08-07EDAC/device_sysfs: Cleanup around edac_device_ctl_poll_msec_store()Borislav Petkov (AMD)
- Align function args - Fix comment style - Fixup formatting around edac_device_reset_delay_period() too The not-too-trivial change is converting the edac_device_reset_delay_period() msec argument to unsigned int as that is what the rest of the code expects. Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
2026-08-07EDAC/device_sysfs: Use kstrtouint() for poll_msec to prevent truncationJad Keskes
The poll_msec sysfs store file uses simple_strtoul() which accepts an unsigned long, but the target field (poll_msec) is unsigned int. On 64-bit systems, a value > UINT_MAX is silently truncated when stored. Fix the mismatch by using kstrtouint() instead. This rejects values larger than UINT_MAX at parse time, making truncation impossible. Also add a check for value < 1 to reject the 0-delay case, which would cause the poll work to spin without delay and consume 100% CPU. Fixes: e27e3dac6517 ("drivers/edac: add edac_device class") Signed-off-by: Jad Keskes <inasj268@gmail.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://patch.msgid.link/20260730145549.148229-1-inasj268@gmail.com
2026-07-30EDAC/igen6: Add Intel Starfire SoCs supportQiuxu Zhuo
Starfire is a derivative of Panther Lake SoC and shares a similar memory subsystem architecture. Add Starfire compute die ID and reuse Panther Lake's configuration data for EDAC support. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Tested-by: Jie Wang <jie.wang@intel.com> Link: https://patch.msgid.link/20260730025454.4099934-1-qiuxu.zhuo@intel.com
2026-07-30EDAC/igen6: Refactor address translation logicQiuxu Zhuo
The igen6 EDAC driver implements similar interleave and hash translation logic at multiple levels of the memory hierarchy. The separate implementations duplicate decoding logic, making future changes harder and increasing the risk of behavior diverging. Consolidate the common address translation operations into shared helpers so all decoding paths use a single implementation. No functional changes intended. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20260730024238.4096623-11-qiuxu.zhuo@intel.com
2026-07-30EDAC/igen6: Remove redundant resource configuration tablesQiuxu Zhuo
Several resource configuration tables differ only in their num_imc value, while all other fields are identical. Their only purpose is to describe the number of memory controllers supported by a platform. Since IMC count is now detected at runtime, these duplicate tables no longer carry any unique platform information. Reuse the shared configurations and remove the redundant tables. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20260730024238.4096623-10-qiuxu.zhuo@intel.com
2026-07-30EDAC/igen6: Detect present memory controllers at runtimeQiuxu Zhuo
The igen6_edac currently relies on res_config::num_imc to describe the number of memory controllers supported by each SoC. As a result, adding support for a new platform requires updating this configuration even though the hardware can be discovered at runtime. Instead, detect the number of present memory controllers at runtime and size the driver state accordingly. This eliminates the need to update res_config whenever a new SoC variant is added. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20260730024238.4096623-9-qiuxu.zhuo@intel.com
2026-07-30EDAC/igen6: Simplify compute die ID commentsQiuxu Zhuo
The existing comments repeat information already implied by the code structure. Shorten them to SoC names only to reduce clutter and improve readability. No functional changes intended. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20260730024238.4096623-8-qiuxu.zhuo@intel.com
2026-07-30EDAC/igen6: Remove unnecessary XOR on the zero-valued interleave bitQiuxu Zhuo
When reconstructing the removed interleave bit from an inflated memory slice address, where a zero was inserted at the interleave bit position, it's unnecessary to XOR this zero-valued interleave bit. Remove this unnecessary XOR operation. No functional changes intended. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20260730024238.4096623-7-qiuxu.zhuo@intel.com
2026-07-30EDAC/igen6: Fix Raptor Lake-P logged error addressQiuxu Zhuo
Raptor Lake-P was treated as using a different IBECC (In-Band ECC) error address format and therefore had a dedicated extraction path that shifted the logged address. However, Raptor Lake-P uses the same cache-line-granularity error address format as other IBECC platforms. The special handling causes the logged address to be decoded incorrectly. Fix the issue by removing Raptor Lake-P specific extraction logic and using the common path instead. This also allows reusing Alder Lake resource configuration data. Fixes: d23627a7688f ("EDAC/igen6: Add Intel Raptor Lake-P SoCs support") Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20260730024238.4096623-6-qiuxu.zhuo@intel.com
2026-07-30EDAC/igen6: Fix channel address decode for non-hash modeQiuxu Zhuo
In non-hash mode, decode_channel_addr() and channel index extraction used a hardcoded interleave bit position 6 instead of the actual intlv_bit parameter, causing incorrect channel address decoding. Fix this by using intlv_bit consistently in both hash and non-hash modes. Fixes: 10590a9d4f23 ("EDAC/igen6: Add EDAC driver for Intel client SoCs using IBECC") Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20260730024238.4096623-5-qiuxu.zhuo@intel.com
2026-07-30EDAC/igen6: Fix channel selection hashQiuxu Zhuo
In channel selection hash mode, the hardware decoding logic always includes the channel interleave bit in XOR operations. However, the hash mask may or may not include this channel interleave bit. When the mask does include this bit, the current igen6_edac code performs XOR on the interleave bit twice, effectively ignoring it - which is incorrect. Fix this issue by ensuring the hash mask always includes the interleave bit, so XOR is performed on the interleave bit exactly once. Fixes: 10590a9d4f23 ("EDAC/igen6: Add EDAC driver for Intel client SoCs using IBECC") Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20260730024238.4096623-4-qiuxu.zhuo@intel.com
2026-07-30EDAC/igen6: Fix interleave boundary conditionQiuxu Zhuo
The address translation logic splits the memory space into interleaved and non-interleaved regions using a boundary at 2 * s_size. The current check uses '>' and incorrectly classifies the boundary address (2 * s_size) as part of the interleaved region. This leads to incorrect channel/sub-channel selection at the region boundary. Fix the classification by using '>=' so that the boundary address is handled in the non-interleaved region, matching the hardware layout. Fixes: 10590a9d4f23 ("EDAC/igen6: Add EDAC driver for Intel client SoCs using IBECC") Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20260730024238.4096623-3-qiuxu.zhuo@intel.com
2026-07-30EDAC/ie31200: Decouple DIMM width decoding from enum orderQiuxu Zhuo
The current method to get DIMM width relied on DEV_* enum ordering via a linear offset (+ DEV_X8), tightly coupling hardware encoding to enum layout. Replace it with explicit decoding to remove this dependency, as the enum is expected to grow with additional device widths. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20260730024238.4096623-2-qiuxu.zhuo@intel.com
2026-07-22EDAC: Remove redundant dev_err()Pan Chuang
Since 55b48e23f5c4 ("genirq/devres: Add error handling in devm_request_*_irq()"), devm_request_irq() and devm_request_threaded_irq() automatically log detailed error messages on failure. Remove the now-redundant driver-specific dev_err() calls. Signed-off-by: Pan Chuang <panchuang@vivo.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> # aspeed Link: https://patch.msgid.link/20260713131510.332386-1-panchuang@vivo.com
2026-07-10EDAC/altera: Remove remaining CONFIG_64BIT ifdefs in the DB-error pathRounak Das
Replace the remaining two CONFIG_64BIT ifdefs with the is_s10 flag, so driver behavior is fully determined by the ECC manager's compatible string rather than the build architecture. These two ifdefs guard the double-bit-error path, where SError handling and the arm_smccc_smc() reboot call are arm64-specific. Switching to is_s10 means s10_edac_dberr_handler() now compiles on 32-bit as well — this is safe because all the symbols it depends on (arm_smccc_smc, INTEL_SIP_SMC_ECC_DBE, and the S10 sysmgr defines) are already available on 32-bit socfpga. Since the function only executes when is_s10 is true, Arria10 behavior is unaffected. This is handled separately from the IRQ-index selection change, as the double-bit-error path is a distinct concern. Signed-off-by: Rounak Das <rounakdas2025@gmail.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Acked-by: Dinh Nguyen <dinguyen@kernel.org> Assisted-by: Claude:claude-sonnet-5 Link: https://patch.msgid.link/20260708091135.94114-3-rounakdas2025@gmail.com
2026-07-10EDAC/altera: Use ECC manager compatible to select A10/S10 IRQ layoutRounak Das
The SDMMC ECC IRQ layout selection uses CONFIG_64BIT to distinguish between Arria10 and Stratix10 paths. Detect the SoC once at probe via the device match table (.data) store it in struct altr_arria10_edac, and use it instead of CONFIG_64BIT. This keeps the decision correct for every ECC child device (OCRAM, SD/MMC, etc.) and avoids any runtime compatible lookup. Signed-off-by: Rounak Das <rounakdas2025@gmail.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Acked-by: Dinh Nguyen <dinguyen@kernel.org> Link: https://patch.msgid.link/20260708091135.94114-2-rounakdas2025@gmail.com
2026-07-07RAS/AMD/ATL, EDAC/amd64: Only load ATL when neededYazen Ghannam
The AMD Address Translation Library (ATL) will attempt to load on all AMD Zen/SMCA systems. However, only systems with DRAM ECC enabled will use the library. Other systems will fail to load the library and produce an unnecessary message to the user. More importantly, that thing is dead code loaded and unused. Remove the ATL module dependency table to prevent autoloading. Request ATL to load from EDAC once all system checks are complete. [ bp: Massage commit message. ] Fixes: 3f3174996be6 ("RAS: Introduce AMD Address Translation Library") Closes: https://lore.kernel.org/20260305154528.1171999-1-mario.limonciello@amd.com Reported-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Tested-by: Deskhmukh Shrirang <Shrirang.Deskhmukh@amd.com> Link: https://lore.kernel.org/all/20260307144910.GA113343@yaz-khff2.amd.com
2026-07-03Replace <linux/mod_devicetable.h> by more specific <linux/device-id/*.h> (c ↵Uwe Kleine-König (The Capable Hub)
files) Replace the #include of <linux/mod_devicetable.h> by the more specific <linux/device-id/*.h> where applicable. For most cases the include can be dropped completely, only a few drivers need one or two headers added. Acked-by: Danilo Krummrich <dakr@kernel.org> Acked-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/1a3f2007c5c5dcf555c09a4035ce3ae8ef1b6c49.1782808461.git.u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com>
2026-07-02EDAC: Stop using 32-bit MSR interfacesJuergen Gross
The 32-bit MSR interfaces rdmsr_safe() and wrmsr_safe() are planned to be removed. Use the related 64-bit variants instead. Signed-off-by: Juergen Gross <jgross@suse.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Cc: Jason Baron <jbaron@akamai.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Yazen Ghannam <yazen.ghannam@amd.com> Cc: linux-edac@vger.kernel.org Link: https://patch.msgid.link/20260629060526.3638272-4-jgross@suse.com
2026-06-30EDAC/sysfs: Use sysfs_emit_at() in dimmdev_location_show()Abhinav Ananthu
Replace the use of scnprintf() with sysfs_emit_at() in dimmdev_location_show() to format the output into the sysfs buffer and thus improve clarity and ensure proper bounds checking in line with the preferred sysfs_emit() API usage for sysfs 'show' functions. No functional change intended. [ bp: Massage commit message. ] Signed-off-by: Abhinav Ananthu <abhinav.ogl@gmail.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Link: https://patch.msgid.link/20250619202133.11843-1-abhinav.ogl@gmail.com
2026-06-29EDAC/debugfs: Remove the fake_inject debugfs interfaceYazen Ghannam
The interface has a potential race condition between a real and fake error when updating the memory controller's error descriptor. There doesn't seem to be an active user base for this interface, so remove it. Closes: https://sashiko.dev/#/patchset/20260518160716.171578-1-yazen.ghannam%40amd.com Reported-by: sashiko-bot <sashiko-bot@kernel.org> Suggested-by: Borislav Petkov <bp@alien8.de> Assisted-by: Claude:claude-opus-4-6 Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/linux-edac/20260611012336.GHaioOGB0NBxv5BZXS@fat_crate.local
2026-05-29EDAC: Consistently define pci_device_ids using named initializersUwe Kleine-König (The Capable Hub)
... and PCI device helpers. The various struct pci_device_id arrays were initialized mostly by one of the PCI_DEVICE macros and then list expressions. The latter aren't easily readable if you're not into PCI. Using named initializers is more explicit and thus easier to parse. Also use PCI_DEVICE* helper macros to assign .vendor, .device, .subvendor and .subdevice where appropriate and skip explicit assignments of 0 (which the compiler takes care of). The secret plan is to make struct pci_device_id::driver_data an anonymous union (similar to https://lore.kernel.org/all/cover.1776579304.git.u.kleine-koenig@baylibre.com/ and that requires named initializers. But it's also a nice cleanup on its own. [ bp: Massage commit message. ] Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Signed-off-by: Tony Luck <tony.luck@intel.com> Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Tested-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Link: https://patch.msgid.link/20260527061057.3796383-2-u.kleine-koenig@baylibre.com
2026-05-29EDAC/igen6: Add Intel Nova Lake-H SoC supportQiuxu Zhuo
Nova Lake-H SoCs share similar memory controller registers and IBECC (In-Band ECC) registers with Panther Lake-H SoCs but use a new memory subsystem register for IBECC presence detection. Add Nova Lake-H SoC compute die IDs and create a new configuration structure for Nova Lake-H SoCs to enable EDAC support. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Tested-by: Jie Wang <jie.wang@intel.com> Link: https://patch.msgid.link/20260521123812.3961038-3-qiuxu.zhuo@intel.com
2026-05-29EDAC/igen6: Make registers for detecting IBECC configurableQiuxu Zhuo
Some Intel CPUs with IBECC (In-Band ECC) capability use different registers to indicate IBECC presence. Make IBECC detection registers CPU-model specific and configure them properly for scalable IBECC detection. No functional changes intended. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Tested-by: Jie Wang <jie.wang@intel.com> Link: https://patch.msgid.link/20260521123812.3961038-2-qiuxu.zhuo@intel.com
2026-05-29EDAC/imh: Add RRL support for Intel Diamond Rapids serverQiuxu Zhuo
Compared to previous generations, Diamond Rapids RRL (Retry Read error Log) operates at DDR sub-channel granularity and adds an extra register per set. It also increases the CORRERRCNT register width from 4 to 8 bytes while reducing the number of registers from 8 to 4. Add the Diamond Rapids RRL register configuration table and enable support. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Tested-by: Yi Lai <yi1.lai@intel.com> Link: https://patch.msgid.link/20260521073112.3881223-9-qiuxu.zhuo@intel.com
2026-05-29EDAC/{skx_common,i10nm}: Prepare RRL for sub-channel granularityQiuxu Zhuo
To prepare for enabling Diamond Rapids server RRL (Retry Read error Log), which operates at sub-channel granularity by converting struct res_config::reg_rrl_ddr from a single pointer to an array (reg_rrl_ddr[2]) and updating all users in i10nm_edac and skx_common accordingly. Initialize only reg_rrl_ddr[0] for existing platforms and prepare for supporting two RRL set groups per DDR channel (one per sub-channel) when present. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Tested-by: Yi Lai <yi1.lai@intel.com> Link: https://patch.msgid.link/20260521073112.3881223-8-qiuxu.zhuo@intel.com
2026-05-29EDAC/skx_common: Add SubChannel support to ADXL decodeQiuxu Zhuo
Diamond Rapids server RRL (Retry Read error Log) operates at sub-channel granularity. Add SubChannel support to ADXL decoding in preparation for enabling this feature. Also introduce adxl_component_required() to validate mandatory ADXL components to improve code readability. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Tested-by: Yi Lai <yi1.lai@intel.com> Link: https://patch.msgid.link/20260521073112.3881223-7-qiuxu.zhuo@intel.com
2026-05-29EDAC/{skx_common,i10nm}: Move RRL handling to common codeQiuxu Zhuo
Move RRL (Retry Read error Log) handling from i10nm_edac to skx_common so it can be shared across EDAC drivers (e.g. imh_edac). - Move RRL enable/disable and log dumping helpers to skx_common to avoid code duplication and enable reuse by other drivers. - Export skx_enable_rrl() and skx_show_rrl() so common RRL handling can be used by i10nm_edac and imh_edac. No functional change intended. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Tested-by: Yi Lai <yi1.lai@intel.com> Link: https://patch.msgid.link/20260521073112.3881223-6-qiuxu.zhuo@intel.com
2026-05-29EDAC/{skx_common,i10nm}: Introduce rrl_ctrl_modeQiuxu Zhuo
RRL (Retry Read error Log) ownership is currently inferred from retry_rd_err_log magic values, making control semantics implicit and harder to understand. Introduce rrl_ctrl_mode to explicitly describe whether RRL is controlled by none, BIOS, or Linux, and replace direct checks with named control states to improve readability and maintainability. No functional change intended. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Tested-by: Yi Lai <yi1.lai@intel.com> Link: https://patch.msgid.link/20260521073112.3881223-5-qiuxu.zhuo@intel.com
2026-05-29EDAC/{skx_common,i10nm}: Rename rrl_mode to rrl_source_typeQiuxu Zhuo
The RRL (Retry Read error Log) values describe where an error was logged from (first/last read and scrub/demand), not an operating mode. Rename rrl_mode to rrl_source_type and "modes" to "sources" to better reflect their meaning and improve code readability. No functional changes intended. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Tested-by: Yi Lai <yi1.lai@intel.com> Link: https://patch.msgid.link/20260521073112.3881223-4-qiuxu.zhuo@intel.com
2026-05-29EDAC/{skx_common,skx,i10nm}: Split skx_set_decode()Qiuxu Zhuo
skx_set_decode() currently handles both address decoding and Retry Read error Log (RRL) reporting, coupling two independent functions in a single API. This complicates setup/teardown and forces callers to update unrelated state. Introduce skx_set_show_rrl() and keep skx_set_decode() focused on decode setup, allowing decode and RRL handling to be managed independently. Also rename the callback type and variable to skx_show_rrl_f and show_rrl for clearer RRL terminology and consistency. No functional changes intended. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Tested-by: Yi Lai <yi1.lai@intel.com> Link: https://patch.msgid.link/20260521073112.3881223-3-qiuxu.zhuo@intel.com
2026-05-29EDAC/{skx_common,i10nm,imh}: Move MC register access helpers to skx_commonQiuxu Zhuo
Both i10nm_basic.c and imh_basic.c use identical helpers for accessing memory controller MMIO-based registers. Move these helpers to skx_common.c to eliminate code duplication. This change also prepares for an upcoming patch that will move RRL(retry_rd_err_log) code from i10nm_basic.c to skx_common.c, which requires these helpers to be available in skx_common.c. Additionally, prefix these function names with 'skx_' to maintain naming consistency within the file. No functional changes intended. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Tested-by: Yi Lai <yi1.lai@intel.com> Link: https://patch.msgid.link/20260521073112.3881223-2-qiuxu.zhuo@intel.com
2026-05-29EDAC/{skx_common,skx}: Fix UBSAN shift-out-of-bounds in skx_get_dimm_infozhoumin
When the skx_get_dimm_attr() helper returns -EINVAL, skx_get_dimm_info() does not validate these return values before using them in a shift operation: size = ((1ull << (rows + cols + ranks)) * banks) >> (20 - 3); If all three values are -22, the shift exponent becomes -66, triggering a UBSAN shift-out-of-bounds error: UBSAN: shift-out-of-bounds in drivers/edac/skx_common.c shift exponent -66 is negative Fixes: 88a242c98740 ("EDAC, skx_common: Separate common code out from skx_edac") Signed-off-by: zhoumin <teczm@foxmail.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/tencent_2A0CC835A18366643CBD2865B169948AB409@qq.com
2026-05-29EDAC/igen6: Add one Intel Panther Lake-H SoC supportQiuxu Zhuo
Add one Intel Panther Lake-H SoC compute die ID for EDAC support. Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20260403054029.3950383-4-qiuxu.zhuo@intel.com
2026-05-29EDAC/igen6: Fix memory topology parsing for Panther Lake-H SoCsQiuxu Zhuo
Panther Lake-H SoC memory controller registers for memory topology have been updated, but the current igen6_edac driver still uses old generation ones to incorrectly parse memory topology. Fix the issue by adding memory topology parsing function pointers to the 'struct res_config' and creating a new configuration structure for Panther Lake-H SoCs to enable igen6_edac to parse memory correctly. Fixes: 0be9f1af3902 ("EDAC/igen6: Add Intel Panther Lake-H SoCs support") Fixes: 4c36e6106997 ("EDAC/igen6: Add more Intel Panther Lake-H SoCs support") Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20260403054029.3950383-3-qiuxu.zhuo@intel.com
2026-05-29EDAC/igen6: Fix call trace due to missing release()Qiuxu Zhuo
When unloading the igen6_edac driver, there is a call trace: Device '(null)' does not have a release() function, it is broken and must be fixed. See Documentation/core-api/kobject.rst. WARNING: drivers/base/core.c:2567 at device_release+0x84/0x90, CPU#5: rmmod/127209 ... RIP: 0010:device_release+0x84/0x90 Call Trace: <TASK> kobject_put+0x8c/0x220 put_device+0x17/0x30 igen6_unregister_mcis+0xa2/0xe0 [igen6_edac] igen6_remove+0x82/0xb0 [igen6_edac] ... Fix the call trace by providing empty release() functions for the memory controller devices. Fixes: 10590a9d4f23 ("EDAC/igen6: Add EDAC driver for Intel client SoCs using IBECC") Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://patch.msgid.link/20260403054029.3950383-2-qiuxu.zhuo@intel.com
2026-05-29EDAC/sb_edac: fix grammar in sb_decode_ddr3 warningThorsten Blum
Fix the warning in sb_decode_ddr3() by adding the missing verb "is" and using "supported" instead of "support" to match the LockStep warning in sb_decode_ddr4(). Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev> Signed-off-by: Tony Luck <tony.luck@intel.com> Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Link: https://patch.msgid.link/20260508143844.2996-3-thorsten.blum@linux.dev
2026-05-29EDAC/i5400: disable error reporting at teardown and refactor helperTushar Tibude
If error reporting is enabled during initialization but initialization fails immediately after, or during normal driver teardown, error reporting is left enabled in the mask register even after exit. Replace i5400_enable_error_reporting() with i5400_set_error_reporting() to combine enabling/disabling. Disable reporting at initialization failure and driver exit, before call to i5400_put_devices() for cleanup. This ensures clean hardware handling by disabling any unused error reporting bits before exiting. Signed-off-by: Tushar Tibude <tushar.tibude1000@gmail.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Link: https://patch.msgid.link/20260430084223.9298-4-tushar.tibude1000@gmail.com
2026-05-29EDAC/i5100: disable error reporting at teardown and create helperTushar Tibude
Error reporting is enabled during init but not reverted when init fails. It is also not disabled at normal driver teardown. Create i5100_set_error_reporting() to enable/disable reporting. Move enable reporting write to after initialization success. Disable reporting at driver teardown. Signed-off-by: Tushar Tibude <tushar.tibude1000@gmail.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Link: https://patch.msgid.link/20260430084223.9298-3-tushar.tibude1000@gmail.com
2026-05-29EDAC/i5000: disable error reporting at teardown and refactor helperTushar Tibude
If error reporting is enabled during initialization but initialization fails immediately after, or during normal driver teardown, error reporting is left enabled in the mask register even after exit. Replace i5000_enable_error_reporting() with i5000_set_error_reporting() to combine enabling/disabling. Disable reporting at initialization failure and driver exit, before call to i5000_put_devices() for cleanup. This ensures clean hardware handling by disabling any unused error reporting bits before exiting. Signed-off-by: Tushar Tibude <tushar.tibude1000@gmail.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Link: https://patch.msgid.link/20260430084223.9298-2-tushar.tibude1000@gmail.com
2026-05-29EDAC/i7300: disable error reporting if init fails and refactor helperTushar Tibude
If error reporting is enabled during initialization but initialization fails immediately after, or during normal driver exit, error reporting is left enabled in the mask register even after exit. Replace i7300_enable_error_reporting() with i7300_set_error_reporting() to combine enabling/disabling. Disable reporting at initialization failure and driver exit, before call to i7300_put_devices() for cleanup. Add enabled reporting flag to i7300_pvt. This ensures clean hardware handling by disabling any unused error reporting bits before exiting. Signed-off-by: Tushar Tibude <tushar.tibude1000@gmail.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Link: https://patch.msgid.link/20260429094806.25097-1-tushar.tibude1000@gmail.com
2026-05-14EDAC/i10nm: Don't fail probing if ADXL is missingVasily Khoruzhick
ADXL is not present in Coreboot- or Slimbootloader-based BIOSes and as result, the driver fails to probe there. Since commit 2738c69a8813 ("EDAC/i10nm: Add driver decoder for Ice Lake and Tremont CPUs"), i10nm_edac supports driver decoder. Switch to driver decoding when ADXL is not present. Signed-off-by: Vasily Khoruzhick <vasilykh@arista.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Cc: stable@vger.kernel.org # v6.1+ Link: https://patch.msgid.link/20260414181735.87023-1-anarsoul@gmail.com
2026-05-05EDAC/versalnet: Fix device name memory leakPrasanna Kumar T S M
The device name allocated via kzalloc() in init_one_mc() is assigned to dev->init_name but never freed on the normal removal path. device_register() copies init_name and then sets dev->init_name to NULL, so the name pointer becomes unreachable from the device. Thus leaking memory. Use a stack-local char array instead of using kzalloc() for name. Fixes: d5fe2fec6c40 ("EDAC: Add a driver for the AMD Versal NET DDR controller") Signed-off-by: Prasanna Kumar T S M <ptsm@linux.microsoft.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Cc: stable@vger.kernel.org Link: https://patch.msgid.link/20260401111856.2342975-1-ptsm@linux.microsoft.com
2026-04-14Merge tag 'ras_core_for_v7.1_rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull RAS updates from Borislav Petkov: - Add new AMD MCA bank names and types to the MCA code, preceded by a clean up of the relevant places to have them more developer-friendly (read: sort them alphanumerically and clean up comments) such that adding new banks is easy * tag 'ras_core_for_v7.1_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/mce, EDAC/mce_amd: Add new SMCA bank types x86/mce, EDAC/mce_amd: Update CS bank type naming x86/mce, EDAC/mce_amd: Reorder SMCA bank type enums
2026-04-14Merge tag 'edac_updates_for_v7.1_rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras Pull EDAC updates from Borislav Petkov: - amd64_edac: Add support for AMD Zen 3 (family 19h, models 40h–4fh) - i10nm: Add GNR error information decoder support as an alternative to the firmware decoder - versalnet: Restructure the init/teardown logic for correct and more readable error handling. Also, fix two memory leaks and a resource leak - Convert several internal structs to use bounded flex arrays, enabling the kernel's runtime checker to catch out-of-bounds memory accesses - Mark various sysfs attribute tables read-only, preventing accidental modification at runtime - The usual fixes and cleanups across the subsystem * tag 'edac_updates_for_v7.1_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras: EDAC/mc: Use kzalloc_flex() EDAC/ie31200: Make rpl_s_cfg static EDAC/i10nm: Fix spelling mistake "readd" -> "read" EDAC/versalnet: Fix device_node leak in mc_probe() EDAC/versalnet: Fix memory leak in remove and probe error paths EDAC/amd64: Add support for family 19h, models 40h-4fh EDAC/i10nm: Add driver decoder for Granite Rapids server EDAC/sb: Use kzalloc_flex() EDAC/i7core: Use kzalloc_flex() EDAC/mpc85xx: Constify device sysfs attributes EDAC/device: Allow addition of const sysfs attributes EDAC/pci_sysfs: Constify instance sysfs attributes EDAC/device: Constify info sysfs attributes EDAC/device: Drop unnecessary and dangerous casts of attributes EDAC/device: Drop unused macro to_edacdev_attr() EDAC/altera: Drop unused field eccmgr_sysfs_attr EDAC/versalnet: Refactor memory controller initialization and cleanup
2026-04-13Merge remote-tracking branches 'ras/edac-misc' and 'ras/edac-drivers' into ↵Borislav Petkov (AMD)
edac-updates * ras/edac-misc: EDAC/mc: Use kzalloc_flex() EDAC/ie31200: Make rpl_s_cfg static EDAC/mpc85xx: Constify device sysfs attributes EDAC/device: Allow addition of const sysfs attributes EDAC/pci_sysfs: Constify instance sysfs attributes EDAC/device: Constify info sysfs attributes EDAC/device: Drop unnecessary and dangerous casts of attributes EDAC/device: Drop unused macro to_edacdev_attr() EDAC/altera: Drop unused field eccmgr_sysfs_attr * ras/edac-drivers: EDAC/i10nm: Fix spelling mistake "readd" -> "read" EDAC/versalnet: Fix device_node leak in mc_probe() EDAC/versalnet: Fix memory leak in remove and probe error paths EDAC/amd64: Add support for family 19h, models 40h-4fh EDAC/i10nm: Add driver decoder for Granite Rapids server EDAC/sb: Use kzalloc_flex() EDAC/i7core: Use kzalloc_flex() EDAC/versalnet: Refactor memory controller initialization and cleanup Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
2026-04-05EDAC/mc: Fix error path ordering in edac_mc_alloc()Borislav Petkov (AMD)
When the mci->pvt_info allocation in edac_mc_alloc() fails, the error path will call put_device() which will end up calling the device's release function. However, the init ordering is wrong such that device_initialize() happens *after* the failed allocation and thus the device itself and the release function pointer are not initialized yet when they're called: MCE: In-kernel MCE decoding enabled. ------------[ cut here ]------------ kobject: '(null)': is not initialized, yet kobject_put() is being called. WARNING: lib/kobject.c:734 at kobject_put, CPU#22: systemd-udevd CPU: 22 UID: 0 PID: 538 Comm: systemd-udevd Not tainted 7.0.0-rc1+ #2 PREEMPT(full) RIP: 0010:kobject_put Call Trace: <TASK> edac_mc_alloc+0xbe/0xe0 [edac_core] amd64_edac_init+0x7a4/0xff0 [amd64_edac] ? __pfx_amd64_edac_init+0x10/0x10 [amd64_edac] do_one_initcall ... Reorder the calling sequence so that the device is initialized and thus the release function pointer is properly set before it can be used. This was found by Claude while reviewing another EDAC patch. Fixes: 0bbb265f7089 ("EDAC/mc: Get rid of silly one-shot struct allocation in edac_mc_alloc()") Reported-by: Claude Code:claude-opus-4.5 Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Cc: stable@kernel.org Link: https://patch.msgid.link/20260331121623.4871-1-bp@kernel.org
generated by cgit v1.2.3 (git 2.25.1) at 2026-09-04 15:06:44 +0000