diff options
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_bw.c | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dram.c | 4 |
2 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 07b4531a4376..18b80147ddc7 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -9,6 +9,7 @@ #include "intel_bw.h" #include "intel_crtc.h" +#include "intel_de.h" #include "intel_display_core.h" #include "intel_display_regs.h" #include "intel_display_types.h" @@ -211,12 +212,11 @@ static int icl_pcode_restrict_qgv_points(struct intel_display *display, static int mtl_read_qgv_point_info(struct intel_display *display, struct intel_qgv_point *sp, int point) { - struct intel_uncore *uncore = to_intel_uncore(display->drm); u32 val, val2; u16 dclk; - val = intel_uncore_read(uncore, MTL_MEM_SS_INFO_QGV_POINT_LOW(point)); - val2 = intel_uncore_read(uncore, MTL_MEM_SS_INFO_QGV_POINT_HIGH(point)); + val = intel_de_read(display, MTL_MEM_SS_INFO_QGV_POINT_LOW(point)); + val2 = intel_de_read(display, MTL_MEM_SS_INFO_QGV_POINT_HIGH(point)); dclk = REG_FIELD_GET(MTL_DCLK_MASK, val); sp->dclk = DIV_ROUND_CLOSEST(16667 * dclk, 1000); sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val); diff --git a/drivers/gpu/drm/i915/display/intel_dram.c b/drivers/gpu/drm/i915/display/intel_dram.c index 1686f808a084..d655ed163f13 100644 --- a/drivers/gpu/drm/i915/display/intel_dram.c +++ b/drivers/gpu/drm/i915/display/intel_dram.c @@ -9,6 +9,7 @@ #include <drm/drm_print.h> #include <drm/intel/intel_pcode_regs.h> +#include "intel_de.h" #include "intel_display_core.h" #include "intel_display_utils.h" #include "intel_display_regs.h" @@ -767,8 +768,7 @@ static int gen12_get_dram_info(struct intel_display *display, struct dram_info * static int xelpdp_get_dram_info(struct intel_display *display, struct dram_info *dram_info) { - struct intel_uncore *uncore = to_intel_uncore(display->drm); - u32 val = intel_uncore_read(uncore, MTL_MEM_SS_INFO_GLOBAL); + u32 val = intel_de_read(display, MTL_MEM_SS_INFO_GLOBAL); switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) { case 0: |