diff options
| author | Esteban Urrutia <esteuwu@proton.me> | 2026-07-15 02:37:47 -0400 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2026-08-07 11:53:37 +0530 |
| commit | f8b4493d5e7e19682abcf538a9faad012b5ef69e (patch) | |
| tree | f037d2b14a9d0ad11a14a834c299bf3010484fa8 /tools/perf/scripts/python | |
| parent | bae047e91213a7b8f86b70f0f48f38374a73d5ea (diff) | |
phy: qcom: qmp-pcie: Add pcs_lane1 offset to V5 offsets
Some SoCs such as SM8475 write data to registers using this offset,
specifically SW_CTRL2 and MX_CTRL2.
Add pcs_lane1 offset to V5 offsets to support this.
Signed-off-by: Esteban Urrutia <esteuwu@proton.me>
Fixes: 0fd0b31965b0 ("phy: qualcomm: qmp-pcie: add support for SAR2130P")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://patch.msgid.link/20260715-sm8475-bup-pcie-v2-2-48bd91a19abf@proton.me
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions