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authorMatt Roper <matthew.d.roper@intel.com>2026-02-27 08:43:41 -0800
committerMatt Roper <matthew.d.roper@intel.com>2026-03-02 12:59:26 -0800
commitd139209ef88e48af1f6731cd45440421c757b6b5 (patch)
tree22fdd5041e49bc12b0975d108584ae29adc19ad9 /tools/perf/scripts/python
parent89340099c6a45884d5bf3995e466359ddb31a6f7 (diff)
drm/xe/xe2_hpg: Correct implementation of Wa_16025250150
Wa_16025250150 asks us to set five register fields of the register to 0x1 each. However we were just OR'ing this into the existing register value (which has a default of 0x4 for each nibble-sized field) resulting in final field values of 0x5 instead of the desired 0x1. Correct the RTP programming (use FIELD_SET instead of SET) to ensure each field is assigned to exactly the value we want. Cc: Aradhya Bhatia <aradhya.bhatia@intel.com> Cc: Tejas Upadhyay <tejas.upadhyay@intel.com> Cc: stable@vger.kernel.org # v6.16+ Fixes: 7654d51f1fd8 ("drm/xe/xe2hpg: Add Wa_16025250150") Reviewed-by: Ngai-Mint Kwan <ngai-mint.kwan@linux.intel.com> Link: https://patch.msgid.link/20260227164341.3600098-2-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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