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| author | Rob Clark <robin.clark@oss.qualcomm.com> | 2026-03-25 11:40:42 -0700 |
|---|---|---|
| committer | Rob Clark <robin.clark@oss.qualcomm.com> | 2026-03-31 13:47:28 -0700 |
| commit | c289a6db9ba6cb974f0317da142e4f665d589566 (patch) | |
| tree | c9f4088852a2affa15d624cd78fc8f1fb678a77e /tools/perf/scripts/python | |
| parent | 85042c2cd970a6b0e686329387096fe19989ae62 (diff) | |
drm/msm/a6xx: Fix HLSQ register dumping
Fix the bitfield offset of HLSQ_READ_SEL state-type bitfield. Otherwise
we are always reading TP state when we wanted SP or HLSQ state.
Reported-by: Connor Abbott <cwabbott0@gmail.com>
Suggested-by: Connor Abbott <cwabbott0@gmail.com>
Fixes: 1707add81551 ("drm/msm/a6xx: Add a6xx gpu state")
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/714236/
Message-ID: <20260325184043.1259312-1-robin.clark@oss.qualcomm.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions