ASoC: ti: davinci-mcasp: improve aux_div selection for mid-range dividers

When the ideal total divider (sysclk/bclk) is between 33 and 4096 and
AUXCLK is enabled, the driver computes aux_div as ceil(div/32) and then
recomputes bclk_div from the truncated sysclk.

This two-step integer division loses precision due to truncation and can
sometimes produce PPM errors large enough for ALSA's hw_rule_format to
reject otherwise valid sample formats.

For example, on AM62D-EVM (auxclk-fs-ratio=2177, tdm-slots=2, fck=96 MHz),
playing S16_LE at 44100 Hz gives BCLK = 1,411,200 Hz and an ideal total
divider of 68.  The old code picks aux_div = ceil(68/32) = 3,
then bclk_div = (96005700/3) / 1411200 = 22, for a total of 3 x 22 =
66 -- two steps from ideal.  The resulting error exceeds the PPM threshold
and causes S16_LE, S24_LE to be rejected.

Therefore when the total divider fits in the AHCLKXDIV register alone
(<=4096), use it directly as aux_div with bclk_div=1, and compare floor
and ceil to pick the closer match, to ensure the best ideal total dividers.

Dividers at or below 32 never enter this path, and dividers above 4096
still fall through to the existing DIV_ROUND_UP path, so previously
working configurations remains unaffected.

Signed-off-by: Sen Wang <sen@ti.com>
Link: https://patch.msgid.link/20260305195825.9998-3-sen@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>

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