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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2026-05-01 11:51:16 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-05-31 10:39:32 +0200 |
| commit | 62169c13d85c143174b61876ff60328b838e02b9 (patch) | |
| tree | 5dc025df8b2830f658d843ef9eb0fcddb324c5d5 /tools/perf/scripts/python | |
| parent | 4c443296ff17f5670ce926f47de8ec5a1f50f857 (diff) | |
arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable PCIe
Enable the PCIE1 slot available on the RZ/V2N EVK.
Note, the PCIE_REFCLK comes from 5L35023B versa clock generator, once the
support for this clock generator is added, the fixed clock node can be
removed and can be replaced with a reference to the clock generator.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260501105116.33452-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions