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authorJiaxing Hu <gahing@gahingwoo.com>2026-07-19 15:46:11 +1200
committerHeiko Stuebner <heiko@sntech.de>2026-07-28 21:12:48 +0200
commit44a48a23974b86d2c551afbabee15ad70b249df5 (patch)
treec43f9d20c40fd3c8370863d2db08451d26fdccc3 /tools/perf/scripts/python
parentf60f44c24b10fe7fd1fa76b360646def1bea193a (diff)
arm64: dts: rockchip: Add ArmSoM CM5 and CM5-IO
Add the ArmSoM CM5, an RK3576 compute module (rk3576-armsom-cm5.dtsi), and its CM5-IO carrier (rk3576-armsom-cm5-io.dts). The module has the RK806 PMIC, HYM8563 RTC, eMMC, GMAC0 with an on-module MotorComm YT8531 PHY, and the SDIO bus for the on-module WiFi. The carrier adds HDMI, a GbE RJ45, two USB-A ports behind a USB3 hub, USB-C with FUSB302 and DP alt-mode, a PCIe 2.0 x1 M.2 slot, microSD, status LEDs and a 40-pin header. The YT8531 has no crystal and takes the SoC 25 MHz reference (REFCLKO25M_GMAC0_OUT), described as a clock on the PHY node and enabled by the PHY driver. The PHY is named explicitly so it is instantiated from the device tree without an MDIO ID probe, which the PHY cannot answer until that clock is running. Its reset is described at the MDIO bus level so mdiobus releases it before the scan. Signed-off-by: Jiaxing Hu <gahing@gahingwoo.com> Link: https://patch.msgid.link/20260719034611.3623066-3-gahing@gahingwoo.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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