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| author | Tejas Upadhyay <tejas.upadhyay@intel.com> | 2026-03-05 17:49:05 +0530 |
|---|---|---|
| committer | Tejas Upadhyay <tejas.upadhyay@intel.com> | 2026-03-23 15:23:24 +0530 |
| commit | 411389d29eab5325e2b250b1cd2ddb567abb7bbb (patch) | |
| tree | 2eaf7a79cba0274da7b6844d63997cc9376ac263 /tools/perf/scripts/python | |
| parent | 4e7ebff69aed345f65f590a17b3119c0cb5eadde (diff) | |
drm/xe/pat: define coh_mode 2way
Defining 2way (two-way coherency) is critical for
Xe3p_LPG (Nova Lake P) platforms to support L2 flush
optimization safely.
This mode allows the driver to skip certain manual cache
flushes (L2 flush optimization) without risking memory
corruption because the hardware ensures the most recent
data is visible to both entities.
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patch.msgid.link/20260305121902.1892593-8-tejas.upadhyay@intel.com
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions