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| author | Varun Gupta <varun.gupta@intel.com> | 2026-03-17 09:34:47 +0530 |
|---|---|---|
| committer | Tejas Upadhyay <tejas.upadhyay@intel.com> | 2026-03-20 15:42:17 +0530 |
| commit | 18fc0f1d7dbeada7810192fe739172c5abd2a902 (patch) | |
| tree | c4f38f8838cae6315bba5c45dd9506fd39aab76a /tools/perf/scripts/python | |
| parent | c56af8fee9ec3124fa6c8cf3d2966070a7aed934 (diff) | |
drm/xe/xe3p_lpg: Add Wa_16029437861
Wa_16029437861 requires disabling COAMA atomics by setting bit 22
(SQ_DISABLE_COAMA) of L3SQCREG2 (0xb104) for Xe3p_LPG graphics
version 35.10 stepping A0..B0. This bit is already set by the existing
Wa_14026144927 entry, so add the new WA ID to the same implementation.
Signed-off-by: Varun Gupta <varun.gupta@intel.com>
Reviewed-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Link: https://patch.msgid.link/20260317040447.1792687-1-varun.gupta@intel.com
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions