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| author | Matthew Leung <matthew.leung@oss.qualcomm.com> | 2026-07-07 20:32:47 +0000 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2026-07-20 16:21:35 +0530 |
| commit | 0696cc735dc7ff53297ad2ee649ceed3b1f93d07 (patch) | |
| tree | d5aa3f0d5042297a676c0dc80e4443f26e461600 /tools/perf/scripts/python | |
| parent | d15224492d1aef8b28508f23b889ee0394b07b83 (diff) | |
phy: qcom-qmp: Add v10 register offsets
Hawi SoC uses v10 register definitions for PCIe Gen3 x2. Add the new
register offset headers for all four sub-blocks:
- QSERDES-COM offsets
- QSERDES TX/RX offsets
- PCS offsets
- PCS PCIe-specific offsets
Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://patch.msgid.link/20260707-hawi-phy-pcie-v4-2-8d9cc6324947@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions