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authorFangyu Yu <fangyu.yu@linux.alibaba.com>2026-01-22 22:32:24 +0800
committerJoerg Roedel <joerg.roedel@amd.com>2026-03-17 13:10:00 +0100
commitf5c262b544975e067ea265fc7403aefbbea8563e (patch)
treed9415a3d4a8b61e455bc41b57b2fd24ff9b79aa4 /tools/perf/scripts/python/stackcollapse.py
parentf338e77383789c0cae23ca3d48adcc5e9e137e3c (diff)
iommu/riscv: Add IOTINVAL after updating DDT/PDT entries
Add riscv_iommu_iodir_iotinval() to perform required TLB and context cache invalidations after updating DDT or PDT entries, as mandated by the RISC-V IOMMU specification (Section 6.3.1 and 6.3.2). Fixes: 488ffbf18171 ("iommu/riscv: Paging domain support") Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com> Reviewed-by: Andrew Jones <andrew.jones@oss.qualcomm.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
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