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| author | Vidya Sagar <vidyas@nvidia.com> | 2026-03-25 00:39:53 +0530 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2026-04-08 17:00:24 -0500 |
| commit | f50e0c7d57b08dfbd6a2aab1eed8f99dd8e81377 (patch) | |
| tree | ad7bbbac8a692dc40fb5916da149704840c5229a /tools/perf/scripts/python/stackcollapse.py | |
| parent | 01d36261ae331583e6bc2034e6aa75c101b83e1d (diff) | |
PCI: tegra194: Calibrate pipe to UPHY for Endpoint mode
Calibrate 'Pipe to Universal PHY(UPHY)' (P2U) for the Endpoint controller
to request UPHY PLL rate change to 2.5GT/s (Gen 1) during initialization.
This helps to reset stale PLL state from the previous bad link state.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
Link: https://patch.msgid.link/20260324191000.1095768-3-mmaddireddy@nvidia.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions