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| author | Matt Roper <matthew.d.roper@intel.com> | 2026-02-05 13:41:41 -0800 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2026-02-06 09:49:20 -0800 |
| commit | e8100643ff01be0fc74048b8296cfb2b9b5c90ed (patch) | |
| tree | e6fcdd9fa86a010ecbef1078b50367716913d6bc /tools/perf/scripts/python/stackcollapse.py | |
| parent | 6acf3d3ed6c1f0febdd046578ea9cafcd47912f4 (diff) | |
drm/xe/xe3p_xpc: XeCore mask spans four registers
On Xe3p_XPC, there are now four registers reserved to express the XeCore
mask rather than just three. Define the new registers and update the IP
descriptor accordingly.
Note that this only applies to Xe3p_XPC for now; Xe3p_LPG still only
uses three registers to express the mask.
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://patch.msgid.link/20260205214139.48515-4-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions