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| author | Jason Gunthorpe <jgg@nvidia.com> | 2026-02-27 11:25:36 -0400 |
|---|---|---|
| committer | Joerg Roedel <joerg.roedel@amd.com> | 2026-03-17 13:14:21 +0100 |
| commit | e71e00127110dedc6a9e746178282b4dac97ed96 (patch) | |
| tree | 4f88c95d9c0ec01406683574112b9c00d5324ba0 /tools/perf/scripts/python/stackcollapse.py | |
| parent | f338e77383789c0cae23ca3d48adcc5e9e137e3c (diff) | |
iommupt: Add the RISC-V page table format
The RISC-V format is a fairly simple 5 level page table not unlike the x86
one. It has optional support for a single contiguous page size of 64k (16
x 4k).
The specification describes a 32-bit format, the general code can support
it via a #define but the iommu side implementation has been left off until
a user comes.
Tested-by: Vincent Chen <vincent.chen@sifive.com>
Acked-by: Paul Walmsley <pjw@kernel.org> # arch/riscv
Reviewed-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Tested-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions
