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| author | Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com> | 2026-03-27 12:14:52 +0530 |
|---|---|---|
| committer | Suraj Kandpal <suraj.kandpal@intel.com> | 2026-03-30 14:46:27 +0530 |
| commit | e2d48e8395a43e8264660ac37a75f7644d4f5d8b (patch) | |
| tree | 49b8e6a96893fd7486e2b535f66eb0a758674efe /tools/perf/scripts/python/stackcollapse.py | |
| parent | e012fa31f90de0928d85ab22d9cc5fc8fe84c5b0 (diff) | |
drm/i915/dmc: Remove invalid PIPEDMC interrupt bits
On display version 35+ PIPEDMC_ATS_FAULT and
PIPEDMC_GTT_FAULT interrupt bits are no longer defined.
Update the interrupt mask to drop these.
Changes in v2:
- Move PIPEDMC_ERROR interrupt enable to a separate patch (Ville Syrjala)
Changes in v3:
- Add Bspec reference (Suraj Kandpal)
Changes in v4:
- Move bspec position in commit message(Suraj Kandpal)
Bspec: 70296
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260327064453.2241523-2-dibin.moolakadan.subrahmanian@intel.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions