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authorRiana Tauro <riana.tauro@intel.com>2026-03-04 13:14:11 +0530
committerRodrigo Vivi <rodrigo.vivi@intel.com>2026-03-05 19:38:56 -0500
commit9b2c89ddd961c188ddd8252a1b01d62ab50f6b95 (patch)
tree2e482b0a8826c188439d8e11f8d2015ac046cd54 /tools/perf/scripts/python/stackcollapse.py
parent63f687362fbabe13006713208bf4131d897b821e (diff)
drm/xe/xe_hw_error: Add support for Core-Compute errors
PVC supports GT error reporting via vector registers along with error status register. Add support to report these errors and update respective counters. Incase of Subslice error reported by vector register, process the error status register for applicable bits. The counter is embedded in the xe drm ras structure and is exposed to the userspace using the drm_ras generic netlink interface. $ sudo ynl --family drm_ras --do get-error-counter \ --json '{"node-id":0, "error-id":1}' {'error-id': 1, 'error-name': 'core-compute', 'error-value': 0} Co-developed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Signed-off-by: Riana Tauro <riana.tauro@intel.com> Reviewed-by: Raag Jadav <raag.jadav@intel.com> Link: https://patch.msgid.link/20260304074412.464435-11-riana.tauro@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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