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authorShengjiu Wang <shengjiu.wang@nxp.com>2026-03-10 18:42:34 +0800
committerMark Brown <broonie@kernel.org>2026-03-10 13:55:58 +0000
commit8e27987a208029c39da7a787bd9f1217d42011a5 (patch)
tree46770d482ce6152a89bd6509ff056ebf605f59f2 /tools/perf/scripts/python/stackcollapse.py
parent819cf1dc01ce66b6906d403a6925c4bd754a7a1d (diff)
ASoC: fsl_sai: add bitcount and timestamp controls
The transmitter and receiver implement separate timestamp counters and bit counters. The bit counter increments at the end of each bit in a frame whenever the transmitter or receiver is enabled. The bit counter can be reset by software. The timestamp counter increments on the bus interface clock whenever it is enabled. The current value of the timestamp counter is latched whenever the bit counter increments. Reading the bit counter register will cause the latched timestamp value to be saved in the bit counter timestamp register. The timestamp counter can be reset by software, this also resets the latched timestamp value and the bit counter timestamp register. The timestamp counter and bit counter can be used by software to track the progress of the transmitter and receiver. It can also be used to calculate the relative frequency of the bit clock against the bus interface clock. These bitcount and timestamp registers are volatile, and supported when the module has timestamp features. Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Link: https://patch.msgid.link/20260310104235.1234569-3-shengjiu.wang@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
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