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| author | Matt Roper <matthew.d.roper@intel.com> | 2026-02-24 15:50:56 -0800 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2026-02-27 08:54:21 -0800 |
| commit | 8ccf5f6b2295164962bbee5b0770f4366fd9bee2 (patch) | |
| tree | 5cac563fd5f09a1bea10a5fbea9a788112fb20d3 /tools/perf/scripts/python/stackcollapse.py | |
| parent | a235e7d0098337c3f2d1e8f3610c719a589e115f (diff) | |
drm/xe/tuning: Apply windower hardware filtering setting on Xe3 and Xe3p
A recent bspec tuning guide update asks us to program
COMMON_SLICE_CHICKEN4[5] on Xe3 and Xe3p platforms. Add this setting to
our LRC tuning RTP table so that the setting will become part of each
context's LRC.
Bspec: 72161, 55902
Reviewed-by: Shuicheng Lin <shuicheng.lin@intel.com>
Link: https://patch.msgid.link/20260224235055.3038710-2-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions