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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-01-06 18:09:51 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-04-27 11:14:30 +0200 |
| commit | 86637727c11a105499e9faa38f3422dfcf4d211d (patch) | |
| tree | cedc558eb7c781c93ad23f875d05a146c8090732 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 254f49634ee16a731174d2ae34bc50bd5f45e731 (diff) | |
arm64: dts: renesas: r8a78000: Fix SCIF brg_int clocks
According to the documentation, the internal clock input for the BRG is
SGASYNCD4_PERW_BUSĪ.
Fixes: c13a643e2c491f5b ("arm64: dts: renesas: Add R8A78000 SoC support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/459d360a8332f92b3766b30814e7e1c76169aaf7.1767719254.git.geert+renesas@glider.be
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions