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authorJames Calligeros <jcalligeros99@gmail.com>2026-03-14 10:27:11 +1000
committerMark Brown <broonie@kernel.org>2026-03-17 18:16:05 +0000
commit4ebaf9d999327ce8e2ea5847ac96fe53fde3fe9a (patch)
treeb0cc6e8f5e9e13921a97e9ce4d0ef720557081ec /tools/perf/scripts/python/stackcollapse.py
parentb7cbc6b8646eec120a652bbfc867e9cc50a14d5f (diff)
ASoC: codecs: cs42l84: set up PLL for more sample rates
Previously, this driver only advertised support for 48 kHz and 96 kHz sample rates, as there was no PLL configuration data specified for any other sample rate/BCLK. The CS42L84 is an Apple-specific variant of CS42L42. The PLL configuration parameters for a variety of common BCLKs are available in the latter's datasheet. What happens if we just use those? As it turns out, they work just fine. Fill out more PLL config parameters in the PLL config lookup table, and advertise the corresponding sample rates to userspace. This enables 44.1, 88.2, 176.4 and 192 kHz output and input. Signed-off-by: James Calligeros <jcalligeros99@gmail.com> Link: https://patch.msgid.link/20260314-cs42l84-rates-v2-1-ea8a5af52542@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
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