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| author | Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> | 2026-04-05 15:39:29 +0200 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2026-04-27 14:32:34 -0500 |
| commit | 46eccc1034c3740b07b58c125190bbb99247c9de (patch) | |
| tree | 5c04fda33b7424aa7178c67609334d0c5ffd9cbc /tools/perf/scripts/python/stackcollapse.py | |
| parent | cd66b6d256f94e40922941e14d7f9390d35d072b (diff) | |
arm64: dts: qcom: glymur: Fix cache and SRAM simple_bus_reg warnings
Correct the unit address of cache controller and SRAM nodes in Qualcomm
Glymur SoC DTSI to fix W=1 DTC warnings:
glymur.dtsi:5876.36-5908.5: Warning (simple_bus_reg): /soc@0/system-cache-controller@20400000: simple-bus unit address format error, expected "21800000"
glymur.dtsi:5917.23-5934.5: Warning (simple_bus_reg): /soc@0/sram@81e08000: simple-bus unit address format error, expected "81e08600"
Fixes: 41b6e8db400c ("arm64: dts: qcom: Introduce Glymur base dtsi")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260405-dts-qcom-w-1-fixes-v2-2-1f2c7b74a93f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions