diff options
| author | Tvrtko Ursulin <tvrtko.ursulin@igalia.com> | 2026-03-24 08:40:10 +0000 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2026-03-24 09:29:11 -0400 |
| commit | 458b1e64e7c0594cca8515fae8996bc52619d2f6 (patch) | |
| tree | d9a58f1936acf665e7e5db97963aeff10fb6cb0d /tools/perf/scripts/python/stackcollapse.py | |
| parent | 88139af77d6acd74bf73f5e36f4bdc63f033f399 (diff) | |
drm/xe/xelp: Quiesce memory traffic before invalidating AuxCCS
According to i915 commit
ad8ebf12217e ("drm/i915/gt: Ensure memory quiesced before invalidation")
quiescing of the memory traffic is required before invalidating the AuxCCS
tables.
Add an extra pipe control flush to achieve that.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patch.msgid.link/20260324084018.20353-5-tvrtko.ursulin@igalia.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions