diff options
| author | Biju Das <biju.das.jz@bp.renesas.com> | 2026-02-03 10:30:11 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-03-06 13:38:54 +0100 |
| commit | 3ac4e6b92fc200e047d13aae06224b2a72539b9e (patch) | |
| tree | 7d25708f187efdd5d736398dea7b84003aab74fc /tools/perf/scripts/python/stackcollapse.py | |
| parent | 56c828dff9ff5e787e74d901e8b530a36b8941da (diff) | |
dt-bindings: soc: renesas: renesas,rzg2l-sysc: Document RZ/G3L SoC
Document RZ/G3L (R9A08G046) SYSC bindings. The SYSC block found on the
RZ/G3L SoC is similar to the one found on RZ/G3S.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260203103031.247435-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions