diff options
| author | Aradhya Bhatia <aradhya.bhatia@intel.com> | 2026-02-06 15:36:07 -0300 |
|---|---|---|
| committer | Gustavo Sousa <gustavo.sousa@intel.com> | 2026-02-10 10:09:17 -0300 |
| commit | 377c89bfaa5d5588214202515d60eacac61395d4 (patch) | |
| tree | 40533963dac0be7f210bfae548d15db53e21cec4 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 1888b3397e11f5663452e0fc14811f9b27d633a2 (diff) | |
drm/xe/xe3p_lpg: Set STLB bank hash mode to 4KB
Since the dominant size of the pages referred in an i-gpu, such as
Xe3p_LPG, will be 4KB, the HW default of mix of 64K and 2M for STLB bank
hash mode does not make sense.
Allow the SW to change it to 4KB Mode, for Xe3p_LPG.
v2:
- Add Bspec reference. (Matt)
Bspec: 78248
Signed-off-by: Aradhya Bhatia <aradhya.bhatia@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20260206-nvl-p-upstreaming-v3-11-636e1ad32688@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions