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| author | Svyatoslav Ryhel <clamor95@gmail.com> | 2026-03-03 10:42:35 +0200 |
|---|---|---|
| committer | Hans Verkuil <hverkuil+cisco@kernel.org> | 2026-03-19 08:18:36 +0100 |
| commit | 071fa83ded5e0d369e3dd2af2afb70e09b39336c (patch) | |
| tree | b1f2c3750cae7eb41604518a9abdc6ab07004932 /tools/perf/scripts/python/stackcollapse.py | |
| parent | d8f8373f1a319830e54791ee0e18aed1e0f2bd56 (diff) | |
staging: media: tegra-video: tegra20: increase maximum VI clock frequency
Increase maximum VI clock frequency to 450MHz to allow correct work with
high resolution camera sensors.
Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # tegra20, parallel camera
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions