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authorDinh Nguyen <dinguyen@kernel.org>2026-06-25 17:17:47 -0500
committerDinh Nguyen <dinguyen@kernel.org>2026-06-29 11:42:06 -0500
commitda07acfd60891b499573b2720b1802a23032472d (patch)
treec6cba21641358dcfd3fb7368ffaf089b4ea4ac69 /tools/perf/scripts/python/bin
parent5eb1916efe763147dfee408e282b77a607aa0c42 (diff)
dt-bindings: net: altr,socfpga-stmmac: add more interrupts for Agilex5
The stmmac hardware on Agilex5 supports 8 TX/RX queue pairs and is dma-coherent. Update the schema to handle the hardware differences between SoC variants. Also make 'interrupts' and 'interrupt-names' as required properties. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v2: Set the top level interrupts to include the widest contraints(1-17) Just have 1 list of all interrupt-names Update commit message to include 'interrupts' and 'interrupt-names' as required properties Change minItems 1 to maxItems 1 for non agilex5 variants Add same constraint for interrupt-names
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