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authorMatt Roper <matthew.d.roper@intel.com>2026-02-10 10:25:19 -0800
committerMatt Roper <matthew.d.roper@intel.com>2026-02-12 11:01:41 -0800
commitb5b55d0932eef682b648e456df177430968e19d5 (patch)
treef05f0f6f68808c48bb817cda5207e07d0332b7ea /tools/perf/scripts/python/bin
parent6d83ef1adaae89c2b85ec486ec90397538deba1b (diff)
drm/xe/xe3p_xpc: Add new XeCore fuse registers to VF runtime regs
SRIOV VFs do not automatically have access to the XeCore fuse registers. Add the two new registers that show up on Xe3p_XPC to the runtime register list to grant VFs access. Since there's a single runtime register list for all Xe3p, this will technically also grant access on Xe3p_LPG platforms where the registers don't exist, but that should be harmless since even if a VF tries to read a non-existent register on those platforms it will just get back a sensible value of 0x0. Fixes: e8100643ff01 ("drm/xe/xe3p_xpc: XeCore mask spans four registers") Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Ngai-Mint Kwan <ngai-mint.kwan@linux.intel.com> Link: https://patch.msgid.link/20260210182519.206952-2-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/bin')
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