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| author | Jouni Högander <jouni.hogander@intel.com> | 2026-03-04 13:30:09 +0200 |
|---|---|---|
| committer | Jouni Högander <jouni.hogander@intel.com> | 2026-03-09 07:23:55 +0200 |
| commit | 24f96d903daf3dcf8fafe84d3d22b80ef47ba493 (patch) | |
| tree | 02b9bc3582db7c1e59d722c38f1d679756190a59 /tools/perf/scripts/python/bin | |
| parent | 681e12440d8b110350a5709101169f319e10ccbb (diff) | |
drm/i915/dsc: Add Selective Update register definitions
Add definitions for DSC_SU_PARAMETER_SET_0_DSC0 and
DSC_SU_PARAMETER_SET_0_DSC1 registers. These are for Selective Update Early
Transport configuration.
Bspec: 71709
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20260304113011.626542-3-jouni.hogander@intel.com
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions