diff options
| author | Kuldeep Singh <kuldeep.singh@oss.qualcomm.com> | 2026-04-02 00:05:10 +0530 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2026-05-12 15:48:16 -0500 |
| commit | 7fb3d0512dacc0d09217eb45057357f00298203d (patch) | |
| tree | 6627925cc932bb02a47523c6a9251e44e8f64d5e /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | fa9c7403af64d3e56a6c20dedc60e0a55b527509 (diff) | |
arm64: dts: qcom: sm8450: Fix ICE reg size
The ICE register region size was originally described incorrectly when
the ICE hardware was first introduced. The same value was later carried
over unchanged when the ICE node was split out from the UFS node into
its own DT entry.
Correct the register size to match the hardware specification.
Fixes: 276ee34a40c1 ("arm64: dts: qcom: sm8450: add Inline Crypto Engine registers and clock")
Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260402-ice_dt_reg_fix-v1-2-74e4c2129238@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions