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| author | Mika Kahola <mika.kahola@intel.com> | 2026-03-12 08:06:35 +0000 |
|---|---|---|
| committer | Mika Kahola <mika.kahola@intel.com> | 2026-03-24 09:45:47 +0200 |
| commit | 78ca669ca5f742eea84495f5f5e2e3c1aed82372 (patch) | |
| tree | 9dbf83563c6b56a3f2c19d637e6a82f56d096fd1 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | 3df7e2feb8f5706eb6d00d043b9613d15c140d38 (diff) | |
drm/i915/lt_phy: Add check if PLL is enabled
Add check for PLL enabling and return early if
PLL is not enabled.
v2: Use PCLK PLL ACK bit to check if PLL is enabled (Suraj)
v3: Check only if PCLK PLL ACK bit for lane 0 is enabled (Suraj)
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260312080657.2648265-3-mika.kahola@intel.com
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions