diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2026-03-30 23:26:28 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2026-03-31 22:08:08 +0300 |
| commit | 3b6e473cdc9c8494a1030fcde5589aa22deb02c9 (patch) | |
| tree | ceac547ebfc6d5961880016e974da5c17360fcf6 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | 299d59abcc3907524239e10277c8dd8b714977e9 (diff) | |
drm/i915/dp: Implement the POST_LT_ADJ_REQ sequence
Implement the POST_LT_ADJ_REQ sequence, which should be used
to further fine tune the link if TPS4 is not supported.
The POST_LT_ADJ_REQ sequence will be performed after
the normal link training has succeeded.
Only the final hop between the last LTTPR and DPRX will
perform the POST_LT_ADJ_REQ adjustment. The earlier hops
will use TPS4 instead since it's mandatory for LTTPRs.
The sequence will terminate when the sink clears the
"in progress" flag, the vswing/pre-emphasis values have
changed six times, or the vswing/pre-emphasis values have
remained unchanged for 200 ms.
Tested-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20260330202629.28616-2-ville.syrjala@linux.intel.com
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions