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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2026-03-26 11:06:38 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-04-27 11:40:52 +0200 |
| commit | d55a0dfec40b6b820a0a391904daf8e74d6f0ec9 (patch) | |
| tree | 2dfb01f31be1b76c7762c02992529bdaf8fe71be /rust/zerocopy/src/pointer/git@git.tavy.me:linux-stable.git | |
| parent | f232745679fe1b8dfc545d2bbb4b5cd1c50b3237 (diff) | |
clk: renesas: r9a08g046: Add GBETH clocks and resets
Add clock and reset entries for the Gigabit Ethernet Interfaces (GBETH
0-1) IPs found on the RZ/G3L SoC. This includes various dividers and
mux clocks needed by these two GBETH IPs. Also add the tx, tx-180, rx,
rx-180, rmii, rmii-tx and rmii-rx clocks to the r9a08g046_no_pm_mod_clk
table to avoid enabling both normal and RMII clocks by the PM framework.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260326110648.29389-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'rust/zerocopy/src/pointer/git@git.tavy.me:linux-stable.git')
0 files changed, 0 insertions, 0 deletions