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| author | John Madieu <john.madieu.xa@bp.renesas.com> | 2026-03-06 15:34:13 +0100 |
|---|---|---|
| committer | Manivannan Sadhasivam <mani@kernel.org> | 2026-03-15 21:04:54 +0530 |
| commit | fabce18494e5a4f388c70a40fa8351c911790d8d (patch) | |
| tree | 6fbea10535494ba647544a8d36a5c9b5717e0cdc /rust/kernel/interop/git@git.tavy.me:linux-stable.git | |
| parent | bb1b0f47f6822864c1689f46348efa42c5d4074c (diff) | |
dt-bindings: PCI: renesas,r9a08g045s33-pcie: Document RZ/G3E SoC
Extend the existing device tree bindings for Renesas RZ/G3S PCIe
controller to include support for the RZ/G3E (renesas,r9a09g047e57-pcie)
PCIe controller. The RZ/G3E PCIe controller is similar to RZ/G3S but has
some key differences:
- Uses a different device ID
- Supports PCIe Gen3 (8.0 GT/s) link speeds
- Uses a different clock naming (clkpmu vs clkl1pm)
- Has a different set of interrupts, interrupt ordering, and reset
signals
Add device tree bindings for renesas,r9a09g047e57-pcie compatible IPs.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> # RZ/V2N EVK
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Link: https://patch.msgid.link/20260306143423.19562-7-john.madieu.xa@bp.renesas.com
Diffstat (limited to 'rust/kernel/interop/git@git.tavy.me:linux-stable.git')
0 files changed, 0 insertions, 0 deletions