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authorThomas Gleixner <tglx@linutronix.de>2025-10-27 09:44:45 +0100
committerIngo Molnar <mingo@kernel.org>2025-11-04 08:32:14 +0100
commit4b7de6df20d43dd651031aef8d818fa5da981dbf (patch)
treeb4a5bc7da9f59d105c1be32f36c0d63e6054c2f5 /kernel/rseq.c
parent4fc9225d19ad6289c03340a520d35e3a6d1aebed (diff)
rseq: Cache CPU ID and MM CID values
In preparation for rewriting RSEQ exit to user space handling provide storage to cache the CPU ID and MM CID values which were written to user space. That prepares for a quick check, which avoids the update when nothing changed. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Link: https://patch.msgid.link/20251027084306.841964081@linutronix.de
Diffstat (limited to 'kernel/rseq.c')
-rw-r--r--kernel/rseq.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/kernel/rseq.c b/kernel/rseq.c
index aae62661e6bb..ad1e7cecd527 100644
--- a/kernel/rseq.c
+++ b/kernel/rseq.c
@@ -184,6 +184,10 @@ static int rseq_update_cpu_node_id(struct task_struct *t)
rseq_unsafe_put_user(t, node_id, node_id, efault_end);
rseq_unsafe_put_user(t, mm_cid, mm_cid, efault_end);
+ /* Cache the user space values */
+ t->rseq.ids.cpu_id = cpu_id;
+ t->rseq.ids.mm_cid = mm_cid;
+
/*
* Additional feature fields added after ORIG_RSEQ_SIZE
* need to be conditionally updated only if