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| author | Akhil P Oommen <akhilpo@oss.qualcomm.com> | 2026-03-27 05:44:01 +0530 |
|---|---|---|
| committer | Rob Clark <robin.clark@oss.qualcomm.com> | 2026-03-31 13:47:30 -0700 |
| commit | 4ac686bfd1929ef659a99f893ebe8faf7f35c76c (patch) | |
| tree | 6acb3d824c54b26412693c0872f0ec104817ae77 /include/linux/i2c/git@git.tavy.me:linux-stable.git | |
| parent | bb79a606321ae63cb086bd34d38de7bb1a1231f7 (diff) | |
drm/msm/a6xx: Add soft fuse detection support
Recent chipsets like Glymur supports a new mechanism for SKU detection.
A new CX_MISC register exposes the combined (or final) speedbin value
from both HW fuse register and the Soft Fuse register. Implement this new
SKU detection along with a new quirk to identify the GPUs that has soft
fuse support.
There is a side effect of this patch on A4x and older series. The
speedbin field in the MSM_PARAM_CHIPID will be 0 instead of 0xffff. This
should be okay as Mesa correctly handles it. Speedbin was not even a
thing when those GPUs' support were added.
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/714676/
Message-ID: <20260327-a8xx-gpu-batch2-v2-12-2b53c38d2101@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Diffstat (limited to 'include/linux/i2c/git@git.tavy.me:linux-stable.git')
0 files changed, 0 insertions, 0 deletions