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authorFabrizio Castro <fabrizio.castro.jz@renesas.com>2026-02-03 12:42:47 +0000
committerGeert Uytterhoeven <geert+renesas@glider.be>2026-03-06 13:33:52 +0100
commit1b4f047dc4010d51821694cc4ed73b52b3040a5c (patch)
tree0b36f19db0da0e5cd2dbbed36cbd25c9613f7e24 /include/linux/i2c/git@git.tavy.me:linux-stable.git
parentdc71d92f0d36dcb68fcf0ef126131a2dedef9393 (diff)
clk: renesas: r9a09g057: Remove entries for WDT{0,2,3}
The HW user manual for the Renesas RZ/V2H(P) SoC specifies that only the WDT1 IP is supposed to be used by Linux, while the WDT{0,2,3} IPs are supposed to be used by the CM33 and CR8 cores. Remove the clock and reset entries for WDT{0,2,3} to prevent interfering with the CM33 and CR8 cores. This change is harmless as only WDT1 is used by Linux, there are no users for the WDT{0,2,3} cores. Fixes: 3aeccbe08171 ("clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT") Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260203124247.7320-4-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'include/linux/i2c/git@git.tavy.me:linux-stable.git')
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