diff options
| author | Stefano Radaelli <stefano.r@variscite.com> | 2026-06-08 16:41:07 +0200 |
|---|---|---|
| committer | Frank Li <Frank.Li@nxp.com> | 2026-06-29 15:16:36 -0400 |
| commit | dd7858bbdfa84beddf7d08bb82eacc8010221493 (patch) | |
| tree | 9065d3855261197370916f9ddd470a79762ec8d8 | |
| parent | 47f8149d31535adafff43ff23084a97600686ddd (diff) | |
arm64: dts: imx8mp-var-som-symphony: enable PCIe
Add the PCIe reference clock and enable the PCIe controller and PHY on
the Symphony carrier board.
Describe the PERST# reset GPIO and configure the PHY to use an external
reference clock input.
Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index fdac4ceb4c19..698f02fc39a5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -48,6 +48,12 @@ }; }; + pcie0_refclk: pcie0-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; @@ -146,6 +152,18 @@ }; }; +&pcie { + reset-gpios = <&pcal6408 1 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie_phy { + clocks = <&pcie0_refclk>; + clock-names = "ref"; + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; |