diff options
| author | Stefano Radaelli <stefano.r@variscite.com> | 2026-06-08 16:41:10 +0200 |
|---|---|---|
| committer | Frank Li <Frank.Li@nxp.com> | 2026-06-29 15:17:19 -0400 |
| commit | c0cb98e3230fd5959bb8075e059fef60d0477698 (patch) | |
| tree | 736e24e9295dedc770990bf922bce43490fad155 | |
| parent | 6651fb350bff74652edf8fdd2193ad33d69a968d (diff) | |
arm64: dts: imx8mp-var-som-symphony: enable ECSPI2
Enable the ECSPI2 bus on the Symphony carrier board and add the pinctrl
configuration for the SPI signals and chip select GPIO.
Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index f8a4b5b2e9fb..387bbe3454c3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -99,6 +99,13 @@ status = "okay"; }; +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + &hdmi_pai { status = "okay"; }; @@ -327,6 +334,15 @@ >; }; + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x12 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x12 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x12 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x12 + >; + }; + pinctrl_hdmi: hdmigrp { fsl,pins = < MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2 |