diff options
| author | Konrad Dybcio <quic_kdybcio@quicinc.com> | 2024-09-19 00:57:17 +0200 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-10-05 21:52:55 -0500 |
| commit | 2b73b83cb82aefb6c907ea91a9977641bbcae683 (patch) | |
| tree | f8f2392ce7e06387f441a35e7f49666a6ec17d55 | |
| parent | 57222f077bd05b6ef8c5b2998400122f3c202e51 (diff) | |
arm64: dts: qcom: sc8280xp: Affirm IDR0.CCTW on apps_smmu
On RPMh-based SoCs, the APPS SMMU advertizes support for cache-coherent
pagetable walk via the IDR0 register. This however is not respected by
the arm-smmu driver unless dma-coherent is set.
Mark the node as dma-coherent to ensure this (and other) implementations
take this coherency into account.
Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org> # Thinkpad X13s (sc8280xp)
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on sdm845-rb3
Link: https://lore.kernel.org/r/20240919-topic-apps_smmu_coherent-v1-4-5b3a8662403d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 80a57aa228397..d36f677ae4cd8 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -5008,6 +5008,7 @@ <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>; + dma-coherent; }; intc: interrupt-controller@17a00000 { |