diff options
Diffstat (limited to 'llvm/utils/TableGen/CodeGenSchedule.cpp')
| -rw-r--r-- | llvm/utils/TableGen/CodeGenSchedule.cpp | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/CodeGenSchedule.cpp index 7c1c37f7b370..e47bda725a17 100644 --- a/llvm/utils/TableGen/CodeGenSchedule.cpp +++ b/llvm/utils/TableGen/CodeGenSchedule.cpp @@ -521,6 +521,15 @@ void CodeGenSchedModels::collectProcModels() { RecVec ProcRecords = Records.getAllDerivedDefinitions("Processor"); llvm::sort(ProcRecords, LessRecordFieldName()); + // Check for duplicated names. + auto I = std::adjacent_find(ProcRecords.begin(), ProcRecords.end(), + [](const Record *Rec1, const Record *Rec2) { + return Rec1->getValueAsString("Name") == Rec2->getValueAsString("Name"); + }); + if (I != ProcRecords.end()) + PrintFatalError((*I)->getLoc(), "Duplicate processor name " + + (*I)->getValueAsString("Name")); + // Reserve space because we can. Reallocation would be ok. ProcModels.reserve(ProcRecords.size()+1); @@ -1973,7 +1982,6 @@ void CodeGenSchedModels::collectProcResources() { void CodeGenSchedModels::checkCompleteness() { bool Complete = true; - bool HadCompleteModel = false; for (const CodeGenProcModel &ProcModel : procModels()) { const bool HasItineraries = ProcModel.hasItineraries(); if (!ProcModel.ModelDef->getValueAsBit("CompleteModel")) @@ -1985,7 +1993,7 @@ void CodeGenSchedModels::checkCompleteness() { continue; unsigned SCIdx = getSchedClassIdx(*Inst); if (!SCIdx) { - if (Inst->TheDef->isValueUnset("SchedRW") && !HadCompleteModel) { + if (Inst->TheDef->isValueUnset("SchedRW")) { PrintError(Inst->TheDef->getLoc(), "No schedule information for instruction '" + Inst->TheDef->getName() + "' in SchedMachineModel '" + @@ -2013,7 +2021,6 @@ void CodeGenSchedModels::checkCompleteness() { Complete = false; } } - HadCompleteModel = true; } if (!Complete) { errs() << "\n\nIncomplete schedule models found.\n" |