From ba4fde74fc7fdd5ef37066a42721f37621cb80f2 Mon Sep 17 00:00:00 2001 From: Tanmay Shah Date: Mon, 14 Nov 2022 15:39:35 -0800 Subject: dt-bindings: remoteproc: Add Xilinx RPU subsystem bindings Xilinx ZynqMP platform has dual-core ARM Cortex R5 Realtime Processing Unit(RPU) subsystem. This patch adds dt-bindings for RPU subsystem (cluster). Signed-off-by: Tanmay Shah Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20221114233940.2096237-2-tanmay.shah@amd.com Signed-off-by: Mathieu Poirier --- include/dt-bindings/power/xlnx-zynqmp-power.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h index 0d9a412fd5e0..618024cbb20d 100644 --- a/include/dt-bindings/power/xlnx-zynqmp-power.h +++ b/include/dt-bindings/power/xlnx-zynqmp-power.h @@ -6,6 +6,12 @@ #ifndef _DT_BINDINGS_ZYNQMP_POWER_H #define _DT_BINDINGS_ZYNQMP_POWER_H +#define PD_RPU_0 7 +#define PD_RPU_1 8 +#define PD_R5_0_ATCM 15 +#define PD_R5_0_BTCM 16 +#define PD_R5_1_ATCM 17 +#define PD_R5_1_BTCM 18 #define PD_USB_0 22 #define PD_USB_1 23 #define PD_TTC_0 24 -- cgit v1.2.3 From b2bd0a8c3ab11f355392c7b81aec5187fc0d562e Mon Sep 17 00:00:00 2001 From: Ben Levinsky Date: Mon, 14 Nov 2022 15:39:37 -0800 Subject: firmware: xilinx: Add ZynqMP firmware ioctl enums for RPU configuration. Add ZynqMP firmware ioctl enums for RPU configuration and TCM Nodes for later use via request_node and release_node Signed-off-by: Ben Levinsky Signed-off-by: Tanmay Shah Acked-by: Michal Simek Link: https://lore.kernel.org/r/20221114233940.2096237-4-tanmay.shah@amd.com Signed-off-by: Mathieu Poirier --- include/linux/firmware/xlnx-zynqmp.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'include') diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 76d2b3ebad84..bdbf855b5eef 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -135,6 +135,10 @@ enum pm_ret_status { }; enum pm_ioctl_id { + IOCTL_GET_RPU_OPER_MODE = 0, + IOCTL_SET_RPU_OPER_MODE = 1, + IOCTL_RPU_BOOT_ADDR_CONFIG = 2, + IOCTL_TCM_COMB_CONFIG = 3, IOCTL_SD_DLL_RESET = 6, IOCTL_SET_SD_TAPDELAY = 7, IOCTL_SET_PLL_FRAC_MODE = 8, @@ -175,6 +179,21 @@ enum pm_query_id { PM_QID_CLOCK_GET_MAX_DIVISOR = 13, }; +enum rpu_oper_mode { + PM_RPU_MODE_LOCKSTEP = 0, + PM_RPU_MODE_SPLIT = 1, +}; + +enum rpu_boot_mem { + PM_RPU_BOOTMEM_LOVEC = 0, + PM_RPU_BOOTMEM_HIVEC = 1, +}; + +enum rpu_tcm_comb { + PM_RPU_TCM_SPLIT = 0, + PM_RPU_TCM_COMB = 1, +}; + enum zynqmp_pm_reset_action { PM_RESET_ACTION_RELEASE = 0, PM_RESET_ACTION_ASSERT = 1, -- cgit v1.2.3 From da22a04f4727694e2c562ae4eb61daf77eef0427 Mon Sep 17 00:00:00 2001 From: Ben Levinsky Date: Mon, 14 Nov 2022 15:39:38 -0800 Subject: firmware: xilinx: Add shutdown/wakeup APIs Add shutdown/wakeup a resource eemi operations to shutdown or bringup a resource. Note alignment of args matches convention of other fn's in this file. The reason being that the long fn name results in aligned args that otherwise go over 80 chars so shift right to avoid this Signed-off-by: Ben Levinsky Signed-off-by: Tanmay Shah Acked-by: Michal Simek Link: https://lore.kernel.org/r/20221114233940.2096237-5-tanmay.shah@amd.com Signed-off-by: Mathieu Poirier --- include/linux/firmware/xlnx-zynqmp.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'include') diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index bdbf855b5eef..ad3f2bd0c470 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -12,6 +12,7 @@ #ifndef __FIRMWARE_ZYNQMP_H__ #define __FIRMWARE_ZYNQMP_H__ +#include #include @@ -87,6 +88,8 @@ enum pm_api_cb_id { enum pm_api_id { PM_GET_API_VERSION = 1, PM_REGISTER_NOTIFIER = 5, + PM_FORCE_POWERDOWN = 8, + PM_REQUEST_WAKEUP = 10, PM_SYSTEM_SHUTDOWN = 12, PM_REQUEST_NODE = 13, PM_RELEASE_NODE = 14, @@ -521,6 +524,12 @@ int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id); int zynqmp_pm_set_feature_config(enum pm_feature_config_id id, u32 value); int zynqmp_pm_get_feature_config(enum pm_feature_config_id id, u32 *payload); int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset); +int zynqmp_pm_force_pwrdwn(const u32 target, + const enum zynqmp_pm_request_ack ack); +int zynqmp_pm_request_wake(const u32 node, + const bool set_addr, + const u64 address, + const enum zynqmp_pm_request_ack ack); int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value); int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config, u32 value); @@ -795,6 +804,20 @@ static inline int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset) return -ENODEV; } +static inline int zynqmp_pm_force_pwrdwn(const u32 target, + const enum zynqmp_pm_request_ack ack) +{ + return -ENODEV; +} + +static inline int zynqmp_pm_request_wake(const u32 node, + const bool set_addr, + const u64 address, + const enum zynqmp_pm_request_ack ack) +{ + return -ENODEV; +} + static inline int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value) -- cgit v1.2.3 From a5e56980cfb7ecaeb9a207c74e2e90ec544f0bc0 Mon Sep 17 00:00:00 2001 From: Ben Levinsky Date: Mon, 14 Nov 2022 15:39:39 -0800 Subject: firmware: xilinx: Add RPU configuration APIs This patch adds APIs to access to configure RPU and its processor-specific memory. That is query the run-time mode of RPU as either split or lockstep as well as API to set this mode. In addition add APIs to access configuration of the RPUs' tightly coupled memory (TCM). Signed-off-by: Ben Levinsky Signed-off-by: Tanmay Shah Acked-by: Michal Simek Link: https://lore.kernel.org/r/20221114233940.2096237-6-tanmay.shah@amd.com Signed-off-by: Mathieu Poirier --- include/linux/firmware/xlnx-zynqmp.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'include') diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index ad3f2bd0c470..cf92e739fa3b 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -530,6 +530,9 @@ int zynqmp_pm_request_wake(const u32 node, const bool set_addr, const u64 address, const enum zynqmp_pm_request_ack ack); +int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode); +int zynqmp_pm_set_rpu_mode(u32 node_id, u32 arg1); +int zynqmp_pm_set_tcm_config(u32 node_id, u32 arg1); int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value); int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config, u32 value); @@ -818,6 +821,21 @@ static inline int zynqmp_pm_request_wake(const u32 node, return -ENODEV; } +static inline int zynqmp_pm_get_rpu_mode(u32 node_id, enum rpu_oper_mode *rpu_mode) +{ + return -ENODEV; +} + +static inline int zynqmp_pm_set_rpu_mode(u32 node_id, u32 arg1) +{ + return -ENODEV; +} + +static inline int zynqmp_pm_set_tcm_config(u32 node_id, u32 arg1) +{ + return -ENODEV; +} + static inline int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value) -- cgit v1.2.3 From 255c4f4a6d5b60cfcd218d8fdae517b886ff155a Mon Sep 17 00:00:00 2001 From: Mike Christie Date: Mon, 21 Nov 2022 21:26:00 -0600 Subject: block: Add error codes for common PR failures If a PR operation fails we can return a device-specific error which is impossible to handle in some cases because we could have a mix of devices when DM is used, or future users like LIO only knows it's interacting with a block device so it doesn't know the type. This patch adds a new pr_status enum so drivers can convert errors to a common type which can be handled by the caller. Signed-off-by: Mike Christie Link: https://lore.kernel.org/r/20221122032603.32766-2-michael.christie@oracle.com Reviewed-by: Christoph Hellwig Reviewed-by: Chaitanya Kulkarni Signed-off-by: Martin K. Petersen --- include/uapi/linux/pr.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'include') diff --git a/include/uapi/linux/pr.h b/include/uapi/linux/pr.h index ccc78cbf1221..d8126415966f 100644 --- a/include/uapi/linux/pr.h +++ b/include/uapi/linux/pr.h @@ -4,6 +4,23 @@ #include +enum pr_status { + PR_STS_SUCCESS = 0x0, + /* + * The following error codes are based on SCSI, because the interface + * was originally created for it and has existing users. + */ + /* Generic device failure. */ + PR_STS_IOERR = 0x2, + PR_STS_RESERVATION_CONFLICT = 0x18, + /* Temporary path failure that can be retried. */ + PR_STS_RETRY_PATH_FAILURE = 0xe0000, + /* The request was failed due to a fast failure timer. */ + PR_STS_PATH_FAST_FAILED = 0xf0000, + /* The path cannot be reached and has been marked as failed. */ + PR_STS_PATH_FAILED = 0x10000, +}; + enum pr_type { PR_WRITE_EXCLUSIVE = 1, PR_EXCLUSIVE_ACCESS = 2, -- cgit v1.2.3 From c9293c1199ecd3cfa07931ec3630f37dba1ca1b8 Mon Sep 17 00:00:00 2001 From: Mike Christie Date: Mon, 21 Nov 2022 21:26:01 -0600 Subject: scsi: core: Rename status_byte to sg_status_byte The next patch adds a helper status_byte function that works like host_byte, so this patch renames the old status_byte to sg_status_byte since it's only used for SG IO. Signed-off-by: Mike Christie Link: https://lore.kernel.org/r/20221122032603.32766-3-michael.christie@oracle.com Reviewed-by: Chaitanya Kulkarni Reviewed-by: Christoph Hellwig Signed-off-by: Martin K. Petersen --- include/scsi/sg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/scsi/sg.h b/include/scsi/sg.h index 068e35d36557..af31cecd9012 100644 --- a/include/scsi/sg.h +++ b/include/scsi/sg.h @@ -159,7 +159,7 @@ struct compat_sg_io_hdr { #define TASK_ABORTED 0x20 /* Obsolete status_byte() declaration */ -#define status_byte(result) (((result) >> 1) & 0x7f) +#define sg_status_byte(result) (((result) >> 1) & 0x7f) typedef struct sg_scsi_id { /* used by SG_GET_SCSI_ID ioctl() */ int host_no; /* as in "scsi" where 'n' is one of 0, 1, 2 etc */ -- cgit v1.2.3 From 04b3c8c0025a1d91a0e133e9b2734a002960f472 Mon Sep 17 00:00:00 2001 From: Mike Christie Date: Mon, 21 Nov 2022 21:26:02 -0600 Subject: scsi: sd: Convert SCSI errors to PR errors This converts the SCSI errors we commonly see during PR handling to PR_STS errors or -Exyz errors. pr_ops callers can then handle SCSI and NVMe errors without knowing the device types. Signed-off-by: Mike Christie Link: https://lore.kernel.org/r/20221122032603.32766-4-michael.christie@oracle.com Reviewed-by: Christoph Hellwig Reviewed-by: Chaitanya Kulkarni Signed-off-by: Martin K. Petersen --- include/scsi/scsi.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/scsi/scsi.h b/include/scsi/scsi.h index 3e46859774c8..ec093594ba53 100644 --- a/include/scsi/scsi.h +++ b/include/scsi/scsi.h @@ -121,6 +121,7 @@ enum scsi_disposition { * msg_byte (unused) * host_byte = set by low-level driver to indicate status. */ +#define status_byte(result) (result & 0xff) #define host_byte(result) (((result) >> 16) & 0xff) #define sense_class(sense) (((sense) >> 4) & 0x7) -- cgit v1.2.3 From 97d73d978271ade27fc751ad606f23c1c4c43678 Mon Sep 17 00:00:00 2001 From: Cezary Rojewski Date: Fri, 2 Dec 2022 16:28:26 +0100 Subject: ALSA: hda: Allow for compress stream to hdac_ext_stream assignment Currently only PCM streams can enlist hdac_stream for their data transfer. Add cstream field to hdac_ext_stream to expose possibility of compress stream assignment in place of PCM one. Limited to HOST-type only as there no other users on the horizon. Signed-off-by: Cezary Rojewski Acked-by: Takashi Iwai Link: https://lore.kernel.org/r/20221202152841.672536-2-cezary.rojewski@intel.com Signed-off-by: Mark Brown --- include/sound/hdaudio_ext.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/sound/hdaudio_ext.h b/include/sound/hdaudio_ext.h index 68ab89211de2..511211f4a2b6 100644 --- a/include/sound/hdaudio_ext.h +++ b/include/sound/hdaudio_ext.h @@ -75,6 +75,8 @@ struct hdac_ext_stream *snd_hdac_ext_stream_assign(struct hdac_bus *bus, struct snd_pcm_substream *substream, int type); void snd_hdac_ext_stream_release(struct hdac_ext_stream *hext_stream, int type); +struct hdac_ext_stream *snd_hdac_ext_cstream_assign(struct hdac_bus *bus, + struct snd_compr_stream *cstream); void snd_hdac_ext_stream_decouple_locked(struct hdac_bus *bus, struct hdac_ext_stream *hext_stream, bool decouple); void snd_hdac_ext_stream_decouple(struct hdac_bus *bus, -- cgit v1.2.3 From 8e4c2eee1e15c1206c26f6b28b05fe9711a427c6 Mon Sep 17 00:00:00 2001 From: Christian Schoenebeck Date: Tue, 22 Nov 2022 20:20:22 +0100 Subject: net/9p: distinguish zero-copy requests Add boolean `zc` member to struct p9_fcall to distinguish zero-copy messages (not using the linear `sdata` buffer for message payload) from regular messages (which do copy message payload to `sdata` before being further processed). This new member is appended to end of structure to avoid inserting huge padding in generated layout. Link: https://lkml.kernel.org/r/8f2a5c12a446c3b544da64e0b1550e1fb2d6f972.1669144861.git.linux_oss@crudebyte.com Signed-off-by: Christian Schoenebeck Tested-by: Stefano Stabellini Signed-off-by: Dominique Martinet --- include/net/9p/9p.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/net/9p/9p.h b/include/net/9p/9p.h index 13abe013af21..429adf6be29c 100644 --- a/include/net/9p/9p.h +++ b/include/net/9p/9p.h @@ -531,6 +531,7 @@ struct p9_rstatfs { * @offset: used by marshalling routines to track current position in buffer * @capacity: used by marshalling routines to track total malloc'd capacity * @sdata: payload + * @zc: whether zero-copy is used * * &p9_fcall represents the structure for all 9P RPC * transactions. Requests are packaged into fcalls, and reponses @@ -549,6 +550,7 @@ struct p9_fcall { struct kmem_cache *cache; u8 *sdata; + bool zc; }; int p9_errstr2errno(char *errstr, int len); -- cgit v1.2.3 From 6c452cff79f8bf1c0146fda598d32061cfd25443 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 2 Dec 2022 19:35:26 +0100 Subject: pwm: Make .get_state() callback return an error code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit .get_state() might fail in some cases. To make it possible that a driver signals such a failure change the prototype of .get_state() to return an error code. This patch was created using coccinelle and the following semantic patch: @p1@ identifier getstatefunc; identifier driver; @@ struct pwm_ops driver = { ..., .get_state = getstatefunc ,... }; @p2@ identifier p1.getstatefunc; identifier chip, pwm, state; @@ -void +int getstatefunc(struct pwm_chip *chip, struct pwm_device *pwm, struct pwm_state *state) { ... - return; + return 0; ... } plus the actual change of the prototype in include/linux/pwm.h (plus some manual fixing of indentions and empty lines). So for now all drivers return success unconditionally. They are adapted in the following patches to make the changes easier reviewable. Reviewed-by: Heiko Stuebner Reviewed-by: Baolin Wang Reviewed-by: Tzung-Bi Shih Reviewed-by: Neil Armstrong Reviewed-by: Nobuhiro Iwamatsu Reviewed-by: Andre Przywara Reviewed-by: Dave Stevenson Acked-by: Douglas Anderson Acked-by: Jernej Skrabec Acked-by: Pavel Machek Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20221130152148.2769768-2-u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König Signed-off-by: Thierry Reding --- include/linux/pwm.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/linux/pwm.h b/include/linux/pwm.h index d70c6e5a839d..4de09163c968 100644 --- a/include/linux/pwm.h +++ b/include/linux/pwm.h @@ -276,8 +276,8 @@ struct pwm_ops { struct pwm_capture *result, unsigned long timeout); int (*apply)(struct pwm_chip *chip, struct pwm_device *pwm, const struct pwm_state *state); - void (*get_state)(struct pwm_chip *chip, struct pwm_device *pwm, - struct pwm_state *state); + int (*get_state)(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state); struct module *owner; }; -- cgit v1.2.3 From 3dae106f4ca358bb1d8d8708d3289fa130b1ad5b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Fri, 2 Dec 2022 19:35:27 +0100 Subject: pwm/tracing: Also record trace events for failed API calls MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Record and report an error code for the events. This allows to report about failed calls without ambiguity and so gives a more complete picture. Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20221130152148.2769768-3-u.kleine-koenig@pengutronix.de Signed-off-by: Uwe Kleine-König Signed-off-by: Thierry Reding --- include/trace/events/pwm.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/include/trace/events/pwm.h b/include/trace/events/pwm.h index cf243de41cc8..12b35e4ff917 100644 --- a/include/trace/events/pwm.h +++ b/include/trace/events/pwm.h @@ -10,9 +10,9 @@ DECLARE_EVENT_CLASS(pwm, - TP_PROTO(struct pwm_device *pwm, const struct pwm_state *state), + TP_PROTO(struct pwm_device *pwm, const struct pwm_state *state, int err), - TP_ARGS(pwm, state), + TP_ARGS(pwm, state, err), TP_STRUCT__entry( __field(struct pwm_device *, pwm) @@ -20,6 +20,7 @@ DECLARE_EVENT_CLASS(pwm, __field(u64, duty_cycle) __field(enum pwm_polarity, polarity) __field(bool, enabled) + __field(int, err) ), TP_fast_assign( @@ -28,28 +29,27 @@ DECLARE_EVENT_CLASS(pwm, __entry->duty_cycle = state->duty_cycle; __entry->polarity = state->polarity; __entry->enabled = state->enabled; + __entry->err = err; ), - TP_printk("%p: period=%llu duty_cycle=%llu polarity=%d enabled=%d", + TP_printk("%p: period=%llu duty_cycle=%llu polarity=%d enabled=%d err=%d", __entry->pwm, __entry->period, __entry->duty_cycle, - __entry->polarity, __entry->enabled) + __entry->polarity, __entry->enabled, __entry->err) ); DEFINE_EVENT(pwm, pwm_apply, - TP_PROTO(struct pwm_device *pwm, const struct pwm_state *state), - - TP_ARGS(pwm, state) + TP_PROTO(struct pwm_device *pwm, const struct pwm_state *state, int err), + TP_ARGS(pwm, state, err) ); DEFINE_EVENT(pwm, pwm_get, - TP_PROTO(struct pwm_device *pwm, const struct pwm_state *state), - - TP_ARGS(pwm, state) + TP_PROTO(struct pwm_device *pwm, const struct pwm_state *state, int err), + TP_ARGS(pwm, state, err) ); #endif /* _TRACE_PWM_H */ -- cgit v1.2.3 From 7ca91a33775c4a33cb451f508f84a7820179c73b Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Sun, 25 Sep 2022 22:44:19 -0700 Subject: mfd: palmas: Stop including of_gpio.h It does not appear that any of palmas sub-drivers are using OF-based gpio APIs, so let's stop including this header. Signed-off-by: Dmitry Torokhov Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20220926054421.1546436-3-dmitry.torokhov@gmail.com --- include/linux/mfd/palmas.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h index 1e61c7e9f50d..117d02708439 100644 --- a/include/linux/mfd/palmas.h +++ b/include/linux/mfd/palmas.h @@ -16,7 +16,6 @@ #include #include #include -#include #include #define PALMAS_NUM_CLIENTS 3 -- cgit v1.2.3 From 3c92699a167a543b2bc7d603e4a09aa78a99f809 Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Sun, 25 Sep 2022 22:44:20 -0700 Subject: mfd: twl6040: Switch to using gpiod API This patch switches the dirver from legacy gpio API to a newer gpiod API so that we can eventually drop the former. Signed-off-by: Dmitry Torokhov Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20220926054421.1546436-4-dmitry.torokhov@gmail.com --- include/linux/mfd/twl6040.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h index 1fc7450bd8ab..cb1e7a9ce317 100644 --- a/include/linux/mfd/twl6040.h +++ b/include/linux/mfd/twl6040.h @@ -196,13 +196,14 @@ struct twl6040_gpo_data { }; struct twl6040_platform_data { - int audpwron_gpio; /* audio power-on gpio */ + struct gpio_desc *audpwron_gpio; /* audio power-on gpio */ struct twl6040_codec_data *codec; struct twl6040_vibra_data *vibra; struct twl6040_gpo_data *gpo; }; +struct gpio_desc; struct regmap; struct regmap_irq_chips_data; @@ -218,7 +219,7 @@ struct twl6040 { struct mfd_cell cells[TWL6040_CELLS]; struct completion ready; - int audpwron; + struct gpio_desc *audpwron; int power_count; int rev; -- cgit v1.2.3 From 1f7caaa1743edbc40f3cd7e2bc0dff89698fd91d Mon Sep 17 00:00:00 2001 From: Dmitry Torokhov Date: Sun, 25 Sep 2022 22:44:21 -0700 Subject: mfd: twl6040: Drop twl6040_platform_data and associated definitions As of df04b6242a58 ("mfd: twl6040: Remove support for legacy (pdata) mode") the driver no longer references the platform data, so we can drop its definition, as well as definitions of related structures. Signed-off-by: Dmitry Torokhov Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20220926054421.1546436-5-dmitry.torokhov@gmail.com --- include/linux/mfd/twl6040.h | 29 ----------------------------- 1 file changed, 29 deletions(-) (limited to 'include') diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h index cb1e7a9ce317..286a724e379a 100644 --- a/include/linux/mfd/twl6040.h +++ b/include/linux/mfd/twl6040.h @@ -174,35 +174,6 @@ #define TWL6040_GPO_MAX 3 -/* TODO: All platform data struct can be removed */ -struct twl6040_codec_data { - u16 hs_left_step; - u16 hs_right_step; - u16 hf_left_step; - u16 hf_right_step; -}; - -struct twl6040_vibra_data { - unsigned int vibldrv_res; /* left driver resistance */ - unsigned int vibrdrv_res; /* right driver resistance */ - unsigned int viblmotor_res; /* left motor resistance */ - unsigned int vibrmotor_res; /* right motor resistance */ - int vddvibl_uV; /* VDDVIBL volt, set 0 for fixed reg */ - int vddvibr_uV; /* VDDVIBR volt, set 0 for fixed reg */ -}; - -struct twl6040_gpo_data { - int gpio_base; -}; - -struct twl6040_platform_data { - struct gpio_desc *audpwron_gpio; /* audio power-on gpio */ - - struct twl6040_codec_data *codec; - struct twl6040_vibra_data *vibra; - struct twl6040_gpo_data *gpo; -}; - struct gpio_desc; struct regmap; struct regmap_irq_chips_data; -- cgit v1.2.3 From fc45720334ebc9f97335a9ce67896811354f0a1c Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 19 Oct 2022 17:29:32 +0200 Subject: mfd: Remove dm355evm_msp driver The DaVinci DM355EVM platform is gone after the removal of all unused board files, so the MTD device along with its sub-devices can be removed as well. Signed-off-by: Arnd Bergmann Acked-by: Bartosz Golaszewski Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20221019152947.3857217-7-arnd@kernel.org --- include/linux/mfd/dm355evm_msp.h | 79 ---------------------------------------- 1 file changed, 79 deletions(-) delete mode 100644 include/linux/mfd/dm355evm_msp.h (limited to 'include') diff --git a/include/linux/mfd/dm355evm_msp.h b/include/linux/mfd/dm355evm_msp.h deleted file mode 100644 index 372470350fab..000000000000 --- a/include/linux/mfd/dm355evm_msp.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * dm355evm_msp.h - support MSP430 microcontroller on DM355EVM board - */ -#ifndef __LINUX_I2C_DM355EVM_MSP -#define __LINUX_I2C_DM355EVM_MSP - -/* - * Written against Spectrum's writeup for the A4 firmware revision, - * and tweaked to match source and rev D2 schematics by removing CPLD - * and NOR flash hooks (which were last appropriate in rev B boards). - * - * Note that the firmware supports a flavor of write posting ... to be - * sure a write completes, issue another read or write. - */ - -/* utilities to access "registers" emulated by msp430 firmware */ -extern int dm355evm_msp_write(u8 value, u8 reg); -extern int dm355evm_msp_read(u8 reg); - - -/* command/control registers */ -#define DM355EVM_MSP_COMMAND 0x00 -# define MSP_COMMAND_NULL 0 -# define MSP_COMMAND_RESET_COLD 1 -# define MSP_COMMAND_RESET_WARM 2 -# define MSP_COMMAND_RESET_WARM_I 3 -# define MSP_COMMAND_POWEROFF 4 -# define MSP_COMMAND_IR_REINIT 5 -#define DM355EVM_MSP_STATUS 0x01 -# define MSP_STATUS_BAD_OFFSET BIT(0) -# define MSP_STATUS_BAD_COMMAND BIT(1) -# define MSP_STATUS_POWER_ERROR BIT(2) -# define MSP_STATUS_RXBUF_OVERRUN BIT(3) -#define DM355EVM_MSP_RESET 0x02 /* 0 bits == in reset */ -# define MSP_RESET_DC5 BIT(0) -# define MSP_RESET_TVP5154 BIT(2) -# define MSP_RESET_IMAGER BIT(3) -# define MSP_RESET_ETHERNET BIT(4) -# define MSP_RESET_SYS BIT(5) -# define MSP_RESET_AIC33 BIT(7) - -/* GPIO registers ... bit patterns mostly match the source MSP ports */ -#define DM355EVM_MSP_LED 0x03 /* active low (MSP P4) */ -#define DM355EVM_MSP_SWITCH1 0x04 /* (MSP P5, masked) */ -# define MSP_SWITCH1_SW6_1 BIT(0) -# define MSP_SWITCH1_SW6_2 BIT(1) -# define MSP_SWITCH1_SW6_3 BIT(2) -# define MSP_SWITCH1_SW6_4 BIT(3) -# define MSP_SWITCH1_J1 BIT(4) /* NTSC/PAL */ -# define MSP_SWITCH1_MSP_INT BIT(5) /* active low */ -#define DM355EVM_MSP_SWITCH2 0x05 /* (MSP P6, masked) */ -# define MSP_SWITCH2_SW10 BIT(3) -# define MSP_SWITCH2_SW11 BIT(4) -# define MSP_SWITCH2_SW12 BIT(5) -# define MSP_SWITCH2_SW13 BIT(6) -# define MSP_SWITCH2_SW14 BIT(7) -#define DM355EVM_MSP_SDMMC 0x06 /* (MSP P2, masked) */ -# define MSP_SDMMC_0_WP BIT(1) -# define MSP_SDMMC_0_CD BIT(2) /* active low */ -# define MSP_SDMMC_1_WP BIT(3) -# define MSP_SDMMC_1_CD BIT(4) /* active low */ -#define DM355EVM_MSP_FIRMREV 0x07 /* not a GPIO (out of order) */ -#define DM355EVM_MSP_VIDEO_IN 0x08 /* (MSP P3, masked) */ -# define MSP_VIDEO_IMAGER BIT(7) /* low == tvp5146 */ - -/* power supply registers are currently omitted */ - -/* RTC registers */ -#define DM355EVM_MSP_RTC_0 0x12 /* LSB */ -#define DM355EVM_MSP_RTC_1 0x13 -#define DM355EVM_MSP_RTC_2 0x14 -#define DM355EVM_MSP_RTC_3 0x15 /* MSB */ - -/* input event queue registers; code == ((HIGH << 8) | LOW) */ -#define DM355EVM_MSP_INPUT_COUNT 0x16 /* decrement by reading LOW */ -#define DM355EVM_MSP_INPUT_HIGH 0x17 -#define DM355EVM_MSP_INPUT_LOW 0x18 - -#endif /* __LINUX_I2C_DM355EVM_MSP */ -- cgit v1.2.3 From 707857d997ae39743eba939a5b3aaafbab04fa78 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 19 Oct 2022 17:03:39 +0200 Subject: mfd: Remove htc-i2cpld driver The HTC Herald machine was removed, so this driver is no longer used anywhere. Cc: Cory Maccarrone Signed-off-by: Arnd Bergmann Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20221019150410.3851944-17-arnd@kernel.org --- include/linux/htcpld.h | 23 ----------------------- 1 file changed, 23 deletions(-) delete mode 100644 include/linux/htcpld.h (limited to 'include') diff --git a/include/linux/htcpld.h b/include/linux/htcpld.h deleted file mode 100644 index 5f8ac9b1d724..000000000000 --- a/include/linux/htcpld.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __LINUX_HTCPLD_H -#define __LINUX_HTCPLD_H - -struct htcpld_chip_platform_data { - unsigned int addr; - unsigned int reset; - unsigned int num_gpios; - unsigned int gpio_out_base; - unsigned int gpio_in_base; - unsigned int irq_base; - unsigned int num_irqs; -}; - -struct htcpld_core_platform_data { - unsigned int i2c_adapter_id; - - struct htcpld_chip_platform_data *chip; - unsigned int num_chip; -}; - -#endif /* __LINUX_HTCPLD_H */ - -- cgit v1.2.3 From 245cb473e5388fcbc01c7284b6a4e1446cdbf054 Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Sun, 23 Oct 2022 10:48:30 +0100 Subject: mfd: pcf50633: Remove #ifdef guards for PM related functions Use the new EXPORT_GPL_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr() macros to handle the .suspend/.resume callbacks. These macros allow the suspend and resume functions to be automatically dropped by the compiler when CONFIG_SUSPEND is disabled, without having to use #ifdef guards. This has the advantage of always compiling these functions in, independently of any Kconfig option. Thanks to that, bugs and other regressions are subsequently easier to catch. Signed-off-by: Paul Cercueil Signed-off-by: Lee Jones --- include/linux/mfd/pcf50633/core.h | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/linux/mfd/pcf50633/core.h b/include/linux/mfd/pcf50633/core.h index 3f752dc62a6c..539f27f8bd89 100644 --- a/include/linux/mfd/pcf50633/core.h +++ b/include/linux/mfd/pcf50633/core.h @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -226,9 +227,6 @@ static inline struct pcf50633 *dev_to_pcf50633(struct device *dev) int pcf50633_irq_init(struct pcf50633 *pcf, int irq); void pcf50633_irq_free(struct pcf50633 *pcf); -#ifdef CONFIG_PM -int pcf50633_irq_suspend(struct pcf50633 *pcf); -int pcf50633_irq_resume(struct pcf50633 *pcf); -#endif +extern const struct dev_pm_ops pcf50633_pm; #endif -- cgit v1.2.3 From 4d8a6ae23af64a37803c0d15922819d27b4b8b08 Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Sun, 23 Oct 2022 10:48:48 +0100 Subject: mfd: stmfx: Remove #ifdef guards for PM related functions Use the new DEFINE_SIMPLE_DEV_PM_OPS() and pm_sleep_ptr() macros to handle the .suspend/.resume callbacks. These macros allow the suspend and resume functions to be automatically dropped by the compiler when CONFIG_SUSPEND is disabled, without having to use #ifdef guards. This has the advantage of always compiling these functions in, independently of any Kconfig option. Thanks to that, bugs and other regressions are subsequently easier to catch. Signed-off-by: Paul Cercueil Signed-off-by: Lee Jones --- include/linux/mfd/stmfx.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/linux/mfd/stmfx.h b/include/linux/mfd/stmfx.h index 744dce63946e..967a2e486800 100644 --- a/include/linux/mfd/stmfx.h +++ b/include/linux/mfd/stmfx.h @@ -113,10 +113,8 @@ struct stmfx { struct irq_domain *irq_domain; struct mutex lock; /* IRQ bus lock */ u8 irq_src; -#ifdef CONFIG_PM u8 bkp_sysctrl; u8 bkp_irqoutpin; -#endif }; int stmfx_function_enable(struct stmfx *stmfx, u32 func); -- cgit v1.2.3 From 74c17a0a49a6ad3b32cb130f25196d1f8d5d560e Mon Sep 17 00:00:00 2001 From: Jerome Neanne Date: Fri, 4 Nov 2022 16:23:09 +0100 Subject: mfd: tps65219: Add driver for TI TPS65219 PMIC The TPS65219 is a power management IC PMIC designed to supply a wide range of SoCs in both portable and stationary applications. Any SoC can control TPS65219 over a standard I2C interface. It contains the following components: - Regulators. - Over Temperature warning and Shut down. - GPIOs - Multi Function Pins (MFP) - power-button This patch adds support for tps65219 PMIC. At this time only the functionalities listed below are made available: - Regulators probe and functionalities - warm and cold reset support - SW shutdown support - Regulator warnings via IRQs - Power-button via IRQ Signed-off-by: Jerome Neanne Signed-off-by: Markus Schneider-Pargmann Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20221104152311.1098603-5-jneanne@baylibre.com --- include/linux/mfd/tps65219.h | 345 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 345 insertions(+) create mode 100644 include/linux/mfd/tps65219.h (limited to 'include') diff --git a/include/linux/mfd/tps65219.h b/include/linux/mfd/tps65219.h new file mode 100644 index 000000000000..e6826e34e2a6 --- /dev/null +++ b/include/linux/mfd/tps65219.h @@ -0,0 +1,345 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Functions to access TPS65219 Power Management IC. + * + * Copyright (C) 2022 BayLibre Incorporated - https://www.baylibre.com/ + */ + +#ifndef MFD_TPS65219_H +#define MFD_TPS65219_H + +#include +#include +#include + +struct regmap; +struct regmap_irq_chip_data; + +#define TPS65219_1V35 1350000 +#define TPS65219_1V8 1800000 + +/* TPS chip id list */ +#define TPS65219 0xF0 + +/* I2C ID for TPS65219 part */ +#define TPS65219_I2C_ID 0x24 + +/* All register addresses */ +#define TPS65219_REG_TI_DEV_ID 0x00 +#define TPS65219_REG_NVM_ID 0x01 +#define TPS65219_REG_ENABLE_CTRL 0x02 +#define TPS65219_REG_BUCKS_CONFIG 0x03 +#define TPS65219_REG_LDO4_VOUT 0x04 +#define TPS65219_REG_LDO3_VOUT 0x05 +#define TPS65219_REG_LDO2_VOUT 0x06 +#define TPS65219_REG_LDO1_VOUT 0x07 +#define TPS65219_REG_BUCK3_VOUT 0x8 +#define TPS65219_REG_BUCK2_VOUT 0x9 +#define TPS65219_REG_BUCK1_VOUT 0xA +#define TPS65219_REG_LDO4_SEQUENCE_SLOT 0xB +#define TPS65219_REG_LDO3_SEQUENCE_SLOT 0xC +#define TPS65219_REG_LDO2_SEQUENCE_SLOT 0xD +#define TPS65219_REG_LDO1_SEQUENCE_SLOT 0xE +#define TPS65219_REG_BUCK3_SEQUENCE_SLOT 0xF +#define TPS65219_REG_BUCK2_SEQUENCE_SLOT 0x10 +#define TPS65219_REG_BUCK1_SEQUENCE_SLOT 0x11 +#define TPS65219_REG_nRST_SEQUENCE_SLOT 0x12 +#define TPS65219_REG_GPIO_SEQUENCE_SLOT 0x13 +#define TPS65219_REG_GPO2_SEQUENCE_SLOT 0x14 +#define TPS65219_REG_GPO1_SEQUENCE_SLOT 0x15 +#define TPS65219_REG_POWER_UP_SLOT_DURATION_1 0x16 +#define TPS65219_REG_POWER_UP_SLOT_DURATION_2 0x17 +#define TPS65219_REG_POWER_UP_SLOT_DURATION_3 0x18 +#define TPS65219_REG_POWER_UP_SLOT_DURATION_4 0x19 +#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_1 0x1A +#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_2 0x1B +#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_3 0x1C +#define TPS65219_REG_POWER_DOWN_SLOT_DURATION_4 0x1D +#define TPS65219_REG_GENERAL_CONFIG 0x1E +#define TPS65219_REG_MFP_1_CONFIG 0x1F +#define TPS65219_REG_MFP_2_CONFIG 0x20 +#define TPS65219_REG_STBY_1_CONFIG 0x21 +#define TPS65219_REG_STBY_2_CONFIG 0x22 +#define TPS65219_REG_OC_DEGL_CONFIG 0x23 +/* 'sub irq' MASK registers */ +#define TPS65219_REG_INT_MASK_UV 0x24 +#define TPS65219_REG_MASK_CONFIG 0x25 + +#define TPS65219_REG_I2C_ADDRESS_REG 0x26 +#define TPS65219_REG_USER_GENERAL_NVM_STORAGE 0x27 +#define TPS65219_REG_MANUFACTURING_VER 0x28 +#define TPS65219_REG_MFP_CTRL 0x29 +#define TPS65219_REG_DISCHARGE_CONFIG 0x2A +/* main irq registers */ +#define TPS65219_REG_INT_SOURCE 0x2B +/* 'sub irq' registers */ +#define TPS65219_REG_INT_LDO_3_4 0x2C +#define TPS65219_REG_INT_LDO_1_2 0x2D +#define TPS65219_REG_INT_BUCK_3 0x2E +#define TPS65219_REG_INT_BUCK_1_2 0x2F +#define TPS65219_REG_INT_SYSTEM 0x30 +#define TPS65219_REG_INT_RV 0x31 +#define TPS65219_REG_INT_TIMEOUT_RV_SD 0x32 +#define TPS65219_REG_INT_PB 0x33 + +#define TPS65219_REG_INT_LDO_3_4_POS 0 +#define TPS65219_REG_INT_LDO_1_2_POS 1 +#define TPS65219_REG_INT_BUCK_3_POS 2 +#define TPS65219_REG_INT_BUCK_1_2_POS 3 +#define TPS65219_REG_INT_SYS_POS 4 +#define TPS65219_REG_INT_RV_POS 5 +#define TPS65219_REG_INT_TO_RV_POS 6 +#define TPS65219_REG_INT_PB_POS 7 + +#define TPS65219_REG_USER_NVM_CMD 0x34 +#define TPS65219_REG_POWER_UP_STATUS 0x35 +#define TPS65219_REG_SPARE_2 0x36 +#define TPS65219_REG_SPARE_3 0x37 +#define TPS65219_REG_FACTORY_CONFIG_2 0x41 + +/* Register field definitions */ +#define TPS65219_DEVID_REV_MASK GENMASK(7, 0) +#define TPS65219_BUCKS_LDOS_VOUT_VSET_MASK GENMASK(5, 0) +#define TPS65219_BUCKS_UV_THR_SEL_MASK BIT(6) +#define TPS65219_BUCKS_BW_SEL_MASK BIT(7) +#define LDO_BYP_SHIFT 6 +#define TPS65219_LDOS_BYP_CONFIG_MASK BIT(LDO_BYP_SHIFT) +#define TPS65219_LDOS_LSW_CONFIG_MASK BIT(7) +/* Regulators enable control */ +#define TPS65219_ENABLE_BUCK1_EN_MASK BIT(0) +#define TPS65219_ENABLE_BUCK2_EN_MASK BIT(1) +#define TPS65219_ENABLE_BUCK3_EN_MASK BIT(2) +#define TPS65219_ENABLE_LDO1_EN_MASK BIT(3) +#define TPS65219_ENABLE_LDO2_EN_MASK BIT(4) +#define TPS65219_ENABLE_LDO3_EN_MASK BIT(5) +#define TPS65219_ENABLE_LDO4_EN_MASK BIT(6) +/* power ON-OFF sequence slot */ +#define TPS65219_BUCKS_LDOS_SEQUENCE_OFF_SLOT_MASK GENMASK(3, 0) +#define TPS65219_BUCKS_LDOS_SEQUENCE_ON_SLOT_MASK GENMASK(7, 4) +/* TODO: Not needed, same mapping as TPS65219_ENABLE_REGNAME_EN, factorize */ +#define TPS65219_STBY1_BUCK1_STBY_EN_MASK BIT(0) +#define TPS65219_STBY1_BUCK2_STBY_EN_MASK BIT(1) +#define TPS65219_STBY1_BUCK3_STBY_EN_MASK BIT(2) +#define TPS65219_STBY1_LDO1_STBY_EN_MASK BIT(3) +#define TPS65219_STBY1_LDO2_STBY_EN_MASK BIT(4) +#define TPS65219_STBY1_LDO3_STBY_EN_MASK BIT(5) +#define TPS65219_STBY1_LDO4_STBY_EN_MASK BIT(6) +/* STBY_2 config */ +#define TPS65219_STBY2_GPO1_STBY_EN_MASK BIT(0) +#define TPS65219_STBY2_GPO2_STBY_EN_MASK BIT(1) +#define TPS65219_STBY2_GPIO_STBY_EN_MASK BIT(2) +/* MFP Control */ +#define TPS65219_MFP_I2C_OFF_REQ_MASK BIT(0) +#define TPS65219_MFP_STBY_I2C_CTRL_MASK BIT(1) +#define TPS65219_MFP_COLD_RESET_I2C_CTRL_MASK BIT(2) +#define TPS65219_MFP_WARM_RESET_I2C_CTRL_MASK BIT(3) +#define TPS65219_MFP_GPIO_STATUS_MASK BIT(4) +/* MFP_1 Config */ +#define TPS65219_MFP_1_VSEL_DDR_SEL_MASK BIT(0) +#define TPS65219_MFP_1_VSEL_SD_POL_MASK BIT(1) +#define TPS65219_MFP_1_VSEL_RAIL_MASK BIT(2) +/* MFP_2 Config */ +#define TPS65219_MFP_2_MODE_STBY_MASK GENMASK(1, 0) +#define TPS65219_MFP_2_MODE_RESET_MASK BIT(2) +#define TPS65219_MFP_2_EN_PB_VSENSE_DEGL_MASK BIT(3) +#define TPS65219_MFP_2_EN_PB_VSENSE_MASK GENMASK(5, 4) +#define TPS65219_MFP_2_WARM_COLD_RESET_MASK BIT(6) +#define TPS65219_MFP_2_PU_ON_FSD_MASK BIT(7) +#define TPS65219_MFP_2_EN 0 +#define TPS65219_MFP_2_PB BIT(4) +#define TPS65219_MFP_2_VSENSE BIT(5) +/* MASK_UV Config */ +#define TPS65219_REG_MASK_UV_LDO1_UV_MASK BIT(0) +#define TPS65219_REG_MASK_UV_LDO2_UV_MASK BIT(1) +#define TPS65219_REG_MASK_UV_LDO3_UV_MASK BIT(2) +#define TPS65219_REG_MASK_UV_LDO4_UV_MASK BIT(3) +#define TPS65219_REG_MASK_UV_BUCK1_UV_MASK BIT(4) +#define TPS65219_REG_MASK_UV_BUCK2_UV_MASK BIT(5) +#define TPS65219_REG_MASK_UV_BUCK3_UV_MASK BIT(6) +#define TPS65219_REG_MASK_UV_RETRY_MASK BIT(7) +/* MASK Config */ +// SENSOR_N_WARM_MASK already defined in Thermal +#define TPS65219_REG_MASK_INT_FOR_RV_MASK BIT(4) +#define TPS65219_REG_MASK_EFFECT_MASK GENMASK(2, 1) +#define TPS65219_REG_MASK_INT_FOR_PB_MASK BIT(7) +/* UnderVoltage - Short to GND - OverCurrent*/ +/* LDO3-4 */ +#define TPS65219_INT_LDO3_SCG_MASK BIT(0) +#define TPS65219_INT_LDO3_OC_MASK BIT(1) +#define TPS65219_INT_LDO3_UV_MASK BIT(2) +#define TPS65219_INT_LDO4_SCG_MASK BIT(3) +#define TPS65219_INT_LDO4_OC_MASK BIT(4) +#define TPS65219_INT_LDO4_UV_MASK BIT(5) +/* LDO1-2 */ +#define TPS65219_INT_LDO1_SCG_MASK BIT(0) +#define TPS65219_INT_LDO1_OC_MASK BIT(1) +#define TPS65219_INT_LDO1_UV_MASK BIT(2) +#define TPS65219_INT_LDO2_SCG_MASK BIT(3) +#define TPS65219_INT_LDO2_OC_MASK BIT(4) +#define TPS65219_INT_LDO2_UV_MASK BIT(5) +/* BUCK3 */ +#define TPS65219_INT_BUCK3_SCG_MASK BIT(0) +#define TPS65219_INT_BUCK3_OC_MASK BIT(1) +#define TPS65219_INT_BUCK3_NEG_OC_MASK BIT(2) +#define TPS65219_INT_BUCK3_UV_MASK BIT(3) +/* BUCK1-2 */ +#define TPS65219_INT_BUCK1_SCG_MASK BIT(0) +#define TPS65219_INT_BUCK1_OC_MASK BIT(1) +#define TPS65219_INT_BUCK1_NEG_OC_MASK BIT(2) +#define TPS65219_INT_BUCK1_UV_MASK BIT(3) +#define TPS65219_INT_BUCK2_SCG_MASK BIT(4) +#define TPS65219_INT_BUCK2_OC_MASK BIT(5) +#define TPS65219_INT_BUCK2_NEG_OC_MASK BIT(6) +#define TPS65219_INT_BUCK2_UV_MASK BIT(7) +/* Thermal Sensor */ +#define TPS65219_INT_SENSOR_3_WARM_MASK BIT(0) +#define TPS65219_INT_SENSOR_2_WARM_MASK BIT(1) +#define TPS65219_INT_SENSOR_1_WARM_MASK BIT(2) +#define TPS65219_INT_SENSOR_0_WARM_MASK BIT(3) +#define TPS65219_INT_SENSOR_3_HOT_MASK BIT(4) +#define TPS65219_INT_SENSOR_2_HOT_MASK BIT(5) +#define TPS65219_INT_SENSOR_1_HOT_MASK BIT(6) +#define TPS65219_INT_SENSOR_0_HOT_MASK BIT(7) +/* Residual Voltage */ +#define TPS65219_INT_BUCK1_RV_MASK BIT(0) +#define TPS65219_INT_BUCK2_RV_MASK BIT(1) +#define TPS65219_INT_BUCK3_RV_MASK BIT(2) +#define TPS65219_INT_LDO1_RV_MASK BIT(3) +#define TPS65219_INT_LDO2_RV_MASK BIT(4) +#define TPS65219_INT_LDO3_RV_MASK BIT(5) +#define TPS65219_INT_LDO4_RV_MASK BIT(6) +/* Residual Voltage ShutDown */ +#define TPS65219_INT_BUCK1_RV_SD_MASK BIT(0) +#define TPS65219_INT_BUCK2_RV_SD_MASK BIT(1) +#define TPS65219_INT_BUCK3_RV_SD_MASK BIT(2) +#define TPS65219_INT_LDO1_RV_SD_MASK BIT(3) +#define TPS65219_INT_LDO2_RV_SD_MASK BIT(4) +#define TPS65219_INT_LDO3_RV_SD_MASK BIT(5) +#define TPS65219_INT_LDO4_RV_SD_MASK BIT(6) +#define TPS65219_INT_TIMEOUT_MASK BIT(7) +/* Power Button */ +#define TPS65219_INT_PB_FALLING_EDGE_DETECT_MASK BIT(0) +#define TPS65219_INT_PB_RISING_EDGE_DETECT_MASK BIT(1) +#define TPS65219_INT_PB_REAL_TIME_STATUS_MASK BIT(2) + +#define TPS65219_PB_POS 7 +#define TPS65219_TO_RV_POS 6 +#define TPS65219_RV_POS 5 +#define TPS65219_SYS_POS 4 +#define TPS65219_BUCK_1_2_POS 3 +#define TPS65219_BUCK_3_POS 2 +#define TPS65219_LDO_1_2_POS 1 +#define TPS65219_LDO_3_4_POS 0 + +/* IRQs */ +enum { + /* LDO3-4 register IRQs */ + TPS65219_INT_LDO3_SCG, + TPS65219_INT_LDO3_OC, + TPS65219_INT_LDO3_UV, + TPS65219_INT_LDO4_SCG, + TPS65219_INT_LDO4_OC, + TPS65219_INT_LDO4_UV, + /* LDO1-2 */ + TPS65219_INT_LDO1_SCG, + TPS65219_INT_LDO1_OC, + TPS65219_INT_LDO1_UV, + TPS65219_INT_LDO2_SCG, + TPS65219_INT_LDO2_OC, + TPS65219_INT_LDO2_UV, + /* BUCK3 */ + TPS65219_INT_BUCK3_SCG, + TPS65219_INT_BUCK3_OC, + TPS65219_INT_BUCK3_NEG_OC, + TPS65219_INT_BUCK3_UV, + /* BUCK1-2 */ + TPS65219_INT_BUCK1_SCG, + TPS65219_INT_BUCK1_OC, + TPS65219_INT_BUCK1_NEG_OC, + TPS65219_INT_BUCK1_UV, + TPS65219_INT_BUCK2_SCG, + TPS65219_INT_BUCK2_OC, + TPS65219_INT_BUCK2_NEG_OC, + TPS65219_INT_BUCK2_UV, + /* Thermal Sensor */ + TPS65219_INT_SENSOR_3_WARM, + TPS65219_INT_SENSOR_2_WARM, + TPS65219_INT_SENSOR_1_WARM, + TPS65219_INT_SENSOR_0_WARM, + TPS65219_INT_SENSOR_3_HOT, + TPS65219_INT_SENSOR_2_HOT, + TPS65219_INT_SENSOR_1_HOT, + TPS65219_INT_SENSOR_0_HOT, + /* Residual Voltage */ + TPS65219_INT_BUCK1_RV, + TPS65219_INT_BUCK2_RV, + TPS65219_INT_BUCK3_RV, + TPS65219_INT_LDO1_RV, + TPS65219_INT_LDO2_RV, + TPS65219_INT_LDO3_RV, + TPS65219_INT_LDO4_RV, + /* Residual Voltage ShutDown */ + TPS65219_INT_BUCK1_RV_SD, + TPS65219_INT_BUCK2_RV_SD, + TPS65219_INT_BUCK3_RV_SD, + TPS65219_INT_LDO1_RV_SD, + TPS65219_INT_LDO2_RV_SD, + TPS65219_INT_LDO3_RV_SD, + TPS65219_INT_LDO4_RV_SD, + TPS65219_INT_TIMEOUT, + /* Power Button */ + TPS65219_INT_PB_FALLING_EDGE_DETECT, + TPS65219_INT_PB_RISING_EDGE_DETECT, +}; + +enum tps65219_regulator_id { + /* DCDC's */ + TPS65219_BUCK_1, + TPS65219_BUCK_2, + TPS65219_BUCK_3, + /* LDOs */ + TPS65219_LDO_1, + TPS65219_LDO_2, + TPS65219_LDO_3, + TPS65219_LDO_4, +}; + +/* Number of step-down converters available */ +#define TPS65219_NUM_DCDC 3 +/* Number of LDO voltage regulators available */ +#define TPS65219_NUM_LDO 4 +/* Number of total regulators available */ +#define TPS65219_NUM_REGULATOR (TPS65219_NUM_DCDC + TPS65219_NUM_LDO) + +/* Define the TPS65219 IRQ numbers */ +enum tps65219_irqs { + /* INT source registers */ + TPS65219_TO_RV_SD_SET_IRQ, + TPS65219_RV_SET_IRQ, + TPS65219_SYS_SET_IRQ, + TPS65219_BUCK_1_2_SET_IRQ, + TPS65219_BUCK_3_SET_IRQ, + TPS65219_LDO_1_2_SET_IRQ, + TPS65219_LDO_3_4_SET_IRQ, + TPS65219_PB_SET_IRQ, +}; + +/** + * struct tps65219 - tps65219 sub-driver chip access routines + * + * Device data may be used to access the TPS65219 chip + * + * @dev: MFD device + * @regmap: Regmap for accessing the device registers + * @irq_data: Regmap irq data used for the irq chip + * @nb: notifier block for the restart handler + */ +struct tps65219 { + struct device *dev; + struct regmap *regmap; + + struct regmap_irq_chip_data *irq_data; + struct notifier_block nb; +}; + +#endif /* MFD_TPS65219_H */ -- cgit v1.2.3 From ee0b089d660021792e4ab4dda191b097ce1e964f Mon Sep 17 00:00:00 2001 From: Kai Vehmanen Date: Fri, 9 Dec 2022 12:18:22 +0200 Subject: ALSA: hda/hdmi: fix stream-id config keep-alive for rt suspend When the new style KAE keep-alive implementation is used on compatible Intel hardware, the clocks are maintained when codec is in D3. The generic code in hda_cleanup_all_streams() can however interfere with generation of audio samples in this mode, by setting the stream and channel ids to zero. To get full benefit of the keepalive, set the new no_stream_clean_at_suspend quirk bit on affected Intel hardware. When this bit is set, stream cleanup is skipped in hda_call_codec_suspend(). Special handling is needed for the case when system goes to suspend. The stream id programming can be lost in this case. This will also cause codec->cvt_setups to be out of sync. Handle this by implementing custom suspend/resume handlers. If keep-alive is active for any converter, set the quirk flags no_stream_clean_at_suspend and forced_resume. Upon resume, keepalive programming is restored if needed. Fixes: 15175a4f2bbb ("ALSA: hda/hdmi: add keep-alive support for ADL-P and DG2") Signed-off-by: Kai Vehmanen Reviewed-by: Pierre-Louis Bossart Link: https://lore.kernel.org/r/20221209101822.3893675-4-kai.vehmanen@linux.intel.com Signed-off-by: Takashi Iwai --- include/sound/hda_codec.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/sound/hda_codec.h b/include/sound/hda_codec.h index 25ec8c181688..eba23daf2c29 100644 --- a/include/sound/hda_codec.h +++ b/include/sound/hda_codec.h @@ -258,6 +258,7 @@ struct hda_codec { unsigned int link_down_at_suspend:1; /* link down at runtime suspend */ unsigned int relaxed_resume:1; /* don't resume forcibly for jack */ unsigned int forced_resume:1; /* forced resume for jack */ + unsigned int no_stream_clean_at_suspend:1; /* do not clean streams at suspend */ #ifdef CONFIG_PM unsigned long power_on_acct; -- cgit v1.2.3 From 0a3212de8ab3e2ce5808c6265855e528d4a6767b Mon Sep 17 00:00:00 2001 From: Naohiro Aota Date: Wed, 14 Dec 2022 11:06:07 +0900 Subject: btrfs: fix trace event name typo for FLUSH_DELAYED_REFS Fix a typo of printing FLUSH_DELAYED_REFS event in flush_space() as FLUSH_ELAYED_REFS. Reviewed-by: Johannes Thumshirn Signed-off-by: Naohiro Aota Reviewed-by: David Sterba Signed-off-by: David Sterba --- include/trace/events/btrfs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/trace/events/btrfs.h b/include/trace/events/btrfs.h index 0bce0b4ff2fa..6548b5b5aa60 100644 --- a/include/trace/events/btrfs.h +++ b/include/trace/events/btrfs.h @@ -98,7 +98,7 @@ struct raid56_bio_trace_info; EM( FLUSH_DELALLOC_WAIT, "FLUSH_DELALLOC_WAIT") \ EM( FLUSH_DELALLOC_FULL, "FLUSH_DELALLOC_FULL") \ EM( FLUSH_DELAYED_REFS_NR, "FLUSH_DELAYED_REFS_NR") \ - EM( FLUSH_DELAYED_REFS, "FLUSH_ELAYED_REFS") \ + EM( FLUSH_DELAYED_REFS, "FLUSH_DELAYED_REFS") \ EM( ALLOC_CHUNK, "ALLOC_CHUNK") \ EM( ALLOC_CHUNK_FORCE, "ALLOC_CHUNK_FORCE") \ EM( RUN_DELAYED_IPUTS, "RUN_DELAYED_IPUTS") \ -- cgit v1.2.3 From 53eab8e76667b124615a943a033cdf97c80c242a Mon Sep 17 00:00:00 2001 From: Jens Axboe Date: Fri, 16 Dec 2022 08:20:31 -0700 Subject: block: don't clear REQ_ALLOC_CACHE for non-polled requests Since commit: b99182c501c3 ("bio: add pcpu caching for non-polling bio_put") we support bio caching for IRQ based IO as well, hence there's no need to manually clear REQ_ALLOC_CACHE if we disable polling on a request. Reviewed-by: Keith Busch Signed-off-by: Jens Axboe --- include/linux/bio.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'include') diff --git a/include/linux/bio.h b/include/linux/bio.h index b231a665682a..22078a28d7cb 100644 --- a/include/linux/bio.h +++ b/include/linux/bio.h @@ -782,8 +782,7 @@ static inline void bio_set_polled(struct bio *bio, struct kiocb *kiocb) static inline void bio_clear_polled(struct bio *bio) { - /* can't support alloc cache if we turn off polling */ - bio->bi_opf &= ~(REQ_POLLED | REQ_ALLOC_CACHE); + bio->bi_opf &= ~REQ_POLLED; } struct bio *blk_next_bio(struct bio *bio, struct block_device *bdev, -- cgit v1.2.3 From 359f608f66b4434fb83b74e23ad14631ea3efc4e Mon Sep 17 00:00:00 2001 From: Elvis Wang Date: Thu, 1 Dec 2022 15:13:15 +0800 Subject: dt-bindings: mailbox: add GCE header file for mt8188 Add Global Command Engine(GCE) header file to define the GCE thread priority, GCE subsys id, event and constant for mt8188. Signed-off-by: Elvis Wang Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Signed-off-by: Jassi Brar --- include/dt-bindings/mailbox/mediatek,mt8188-gce.h | 967 ++++++++++++++++++++++ 1 file changed, 967 insertions(+) create mode 100644 include/dt-bindings/mailbox/mediatek,mt8188-gce.h (limited to 'include') diff --git a/include/dt-bindings/mailbox/mediatek,mt8188-gce.h b/include/dt-bindings/mailbox/mediatek,mt8188-gce.h new file mode 100644 index 000000000000..119865787b47 --- /dev/null +++ b/include/dt-bindings/mailbox/mediatek,mt8188-gce.h @@ -0,0 +1,967 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (c) 2022 MediaTek Inc. + * + */ +#ifndef _DT_BINDINGS_GCE_MT8188_H +#define _DT_BINDINGS_GCE_MT8188_H + +#define CMDQ_THR_PRIO_LOWEST 0 +#define CMDQ_THR_PRIO_1 1 +#define CMDQ_THR_PRIO_2 2 +#define CMDQ_THR_PRIO_3 3 +#define CMDQ_THR_PRIO_4 4 +#define CMDQ_THR_PRIO_5 5 +#define CMDQ_THR_PRIO_6 6 +#define CMDQ_THR_PRIO_HIGHEST 7 + +#define SUBSYS_1400XXXX 0 +#define SUBSYS_1401XXXX 1 +#define SUBSYS_1402XXXX 2 +#define SUBSYS_1c00XXXX 3 +#define SUBSYS_1c01XXXX 4 +#define SUBSYS_1c02XXXX 5 +#define SUBSYS_1c10XXXX 6 +#define SUBSYS_1c11XXXX 7 +#define SUBSYS_1c12XXXX 8 +#define SUBSYS_14f0XXXX 9 +#define SUBSYS_14f1XXXX 10 +#define SUBSYS_14f2XXXX 11 +#define SUBSYS_1800XXXX 12 +#define SUBSYS_1801XXXX 13 +#define SUBSYS_1802XXXX 14 +#define SUBSYS_1803XXXX 15 +#define SUBSYS_1032XXXX 16 +#define SUBSYS_1033XXXX 17 +#define SUBSYS_1600XXXX 18 +#define SUBSYS_1601XXXX 19 +#define SUBSYS_14e0XXXX 20 +#define SUBSYS_1c20XXXX 21 +#define SUBSYS_1c30XXXX 22 +#define SUBSYS_1c40XXXX 23 +#define SUBSYS_1c50XXXX 24 +#define SUBSYS_1c60XXXX 25 +#define SUBSYS_NO_SUPPORT 99 + +#define CMDQ_EVENT_IMG_SOF 0 +#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_0 1 +#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_1 2 +#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_2 3 +#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_3 4 +#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_4 5 +#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_5 6 +#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_6 7 +#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_7 8 +#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_8 9 +#define CMDQ_EVENT_IMG_TRAW0_CQ_THR_DONE_9 10 +#define CMDQ_EVENT_IMG_TRAW0_DMA_ERROR_INT 11 +#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_0 12 +#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_1 13 +#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_2 14 +#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_3 15 +#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_4 16 +#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_5 17 +#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_6 18 +#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_7 19 +#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_8 20 +#define CMDQ_EVENT_IMG_TRAW1_CQ_THR_DONE_9 21 +#define CMDQ_EVENT_IMG_TRAW1_DMA_ERROR_INT 22 +#define CMDQ_EVENT_IMG_ADL_RESERVED 23 +#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_0 24 +#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_1 25 +#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_2 26 +#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_3 27 +#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_4 28 +#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_5 29 +#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_6 30 +#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_7 31 +#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_8 32 +#define CMDQ_EVENT_IMG_DIP_CQ_THR_DONE_9 33 +#define CMDQ_EVENT_IMG_DIP_DMA_ERR 34 +#define CMDQ_EVENT_IMG_DIP_NR_DMA_ERR 35 +#define CMDQ_EVENT_DIP_DUMMY_0 36 +#define CMDQ_EVENT_DIP_DUMMY_1 37 +#define CMDQ_EVENT_DIP_DUMMY_2 38 +#define CMDQ_EVENT_IMG_WPE_EIS_GCE_FRAME_DONE 39 +#define CMDQ_EVENT_IMG_WPE_EIS_DONE_SYNC_OUT 40 +#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_0 41 +#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_1 42 +#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_2 43 +#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_3 44 +#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_4 45 +#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_5 46 +#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_6 47 +#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_7 48 +#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_8 49 +#define CMDQ_EVENT_IMG_WPE_EIS_CQ_THR_DONE_9 50 +#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_0 51 +#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_1 52 +#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_2 53 +#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_3 54 +#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_4 55 +#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_5 56 +#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_6 57 +#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_7 58 +#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_8 59 +#define CMDQ_EVENT_IMG_PQDIP_A_CQ_THR_DONE_9 60 +#define CMDQ_EVENT_IMG_PQDIP_A_DMA_ERR 61 +#define CMDQ_EVENT_WPE0_DUMMY_0 62 +#define CMDQ_EVENT_WPE0_DUMMY_1 63 +#define CMDQ_EVENT_WPE0_DUMMY_2 64 +#define CMDQ_EVENT_IMG_WPE_TNR_GCE_FRAME_DONE 65 +#define CMDQ_EVENT_IMG_WPE_TNR_DONE_SYNC_OUT 66 +#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_0 67 +#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_1 68 +#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_2 69 +#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_3 70 +#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_4 71 +#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_5 72 +#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_6 73 +#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_7 74 +#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_8 75 +#define CMDQ_EVENT_IMG_WPE_TNR_CQ_THR_DONE_9 76 +#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_0 77 +#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_1 78 +#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_2 79 +#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_3 80 +#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_4 81 +#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_5 82 +#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_6 83 +#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_7 84 +#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_8 85 +#define CMDQ_EVENT_IMG_PQDIP_B_CQ_THR_DONE_9 86 +#define CMDQ_EVENT_IMG_PQDIP_B_DMA_ERR 87 +#define CMDQ_EVENT_WPE1_DUMMY_0 88 +#define CMDQ_EVENT_WPE1_DUMMY_1 89 +#define CMDQ_EVENT_WPE1_DUMMY_2 90 +#define CMDQ_EVENT_IMG_WPE_LITE_GCE_FRAME_DONE 91 +#define CMDQ_EVENT_IMG_WPE_LITE_DONE_SYNC_OUT 92 +#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_0 93 +#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_1 94 +#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_2 95 +#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_3 96 +#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_4 97 +#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_5 98 +#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_6 99 +#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_7 100 +#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_8 101 +#define CMDQ_EVENT_IMG_WPE_LITE_CQ_THR_DONE_9 102 +#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_0 103 +#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_1 104 +#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_2 105 +#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_3 106 +#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_4 107 +#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_5 108 +#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_6 109 +#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_7 110 +#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_8 111 +#define CMDQ_EVENT_IMG_XTRAW_CQ_THR_DONE_9 112 +#define CMDQ_EVENT_IMG_XTRAW_DMA_ERR_EVENT 113 +#define CMDQ_EVENT_WPE2_DUMMY_0 114 +#define CMDQ_EVENT_WPE2_DUMMY_1 115 +#define CMDQ_EVENT_WPE2_DUMMY_2 116 +#define CMDQ_EVENT_IMG_IMGSYS_IPE_DUMMY 117 +#define CMDQ_EVENT_IMG_IMGSYS_IPE_FDVT_DONE 118 +#define CMDQ_EVENT_IMG_IMGSYS_IPE_ME_DONE 119 +#define CMDQ_EVENT_IMG_IMGSYS_IPE_DVS_DONE 120 +#define CMDQ_EVENT_IMG_IMGSYS_IPE_DVP_DONE 121 +#define CMDQ_EVENT_FDVT1_RESERVED 122 +#define CMDQ_EVENT_IMG_ENG_EVENT 123 +#define CMDQ_EVENT_CAMSUBA_SW_PASS1_DONE 129 +#define CMDQ_EVENT_CAMSUBB_SW_PASS1_DONE 130 +#define CMDQ_EVENT_CAMSUBC_SW_PASS1_DONE 131 +#define CMDQ_EVENT_GCAMSV_A_1_SW_PASS1_DONE 132 +#define CMDQ_EVENT_GCAMSV_A_2_SW_PASS1_DONE 133 +#define CMDQ_EVENT_GCAMSV_B_1_SW_PASS1_DONE 134 +#define CMDQ_EVENT_GCAMSV_B_2_SW_PASS1_DONE 135 +#define CMDQ_EVENT_GCAMSV_C_1_SW_PASS1_DONE 136 +#define CMDQ_EVENT_GCAMSV_C_2_SW_PASS1_DONE 137 +#define CMDQ_EVENT_GCAMSV_D_1_SW_PASS1_DONE 138 +#define CMDQ_EVENT_GCAMSV_D_2_SW_PASS1_DONE 139 +#define CMDQ_EVENT_GCAMSV_E_1_SW_PASS1_DONE 140 +#define CMDQ_EVENT_GCAMSV_E_2_SW_PASS1_DONE 141 +#define CMDQ_EVENT_GCAMSV_F_1_SW_PASS1_DONE 142 +#define CMDQ_EVENT_GCAMSV_F_2_SW_PASS1_DONE 143 +#define CMDQ_EVENT_GCAMSV_G_1_SW_PASS1_DONE 144 +#define CMDQ_EVENT_GCAMSV_G_2_SW_PASS1_DONE 145 +#define CMDQ_EVENT_GCAMSV_H_1_SW_PASS1_DONE 146 +#define CMDQ_EVENT_GCAMSV_H_2_SW_PASS1_DONE 147 +#define CMDQ_EVENT_GCAMSV_I_1_SW_PASS1_DONE 148 +#define CMDQ_EVENT_GCAMSV_I_2_SW_PASS1_DONE 149 +#define CMDQ_EVENT_GCAMSV_J_1_SW_PASS1_DONE 150 +#define CMDQ_EVENT_GCAMSV_J_2_SW_PASS1_DONE 151 +#define CMDQ_EVENT_MRAW_0_SW_PASS1_DONE 152 +#define CMDQ_EVENT_MRAW_1_SW_PASS1_DONE 153 +#define CMDQ_EVENT_MRAW_2_SW_PASS1_DONE 154 +#define CMDQ_EVENT_MRAW_3_SW_PASS1_DONE 155 +#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 156 +#define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL 157 +#define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 158 +#define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 159 +#define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 160 +#define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 161 +#define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 162 +#define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 163 +#define CMDQ_EVENT_SENINF_CAM8_FIFO_FULL 164 +#define CMDQ_EVENT_SENINF_CAM9_FIFO_FULL 165 +#define CMDQ_EVENT_SENINF_CAM10_FIFO_FULL 166 +#define CMDQ_EVENT_SENINF_CAM11_FIFO_FULL 167 +#define CMDQ_EVENT_SENINF_CAM12_FIFO_FULL 168 +#define CMDQ_EVENT_SENINF_CAM13_FIFO_FULL 169 +#define CMDQ_EVENT_SENINF_CAM14_FIFO_FULL 170 +#define CMDQ_EVENT_SENINF_CAM15_FIFO_FULL 171 +#define CMDQ_EVENT_SENINF_CAM16_FIFO_FULL 172 +#define CMDQ_EVENT_SENINF_CAM17_FIFO_FULL 173 +#define CMDQ_EVENT_SENINF_CAM18_FIFO_FULL 174 +#define CMDQ_EVENT_SENINF_CAM19_FIFO_FULL 175 +#define CMDQ_EVENT_SENINF_CAM20_FIFO_FULL 176 +#define CMDQ_EVENT_SENINF_CAM21_FIFO_FULL 177 +#define CMDQ_EVENT_SENINF_CAM22_FIFO_FULL 178 +#define CMDQ_EVENT_SENINF_CAM23_FIFO_FULL 179 +#define CMDQ_EVENT_SENINF_CAM24_FIFO_FULL 180 +#define CMDQ_EVENT_SENINF_CAM25_FIFO_FULL 181 +#define CMDQ_EVENT_SENINF_CAM26_FIFO_FULL 182 +#define CMDQ_EVENT_TG_OVRUN_MRAW0_INT 183 +#define CMDQ_EVENT_TG_OVRUN_MRAW1_INT 184 +#define CMDQ_EVENT_TG_OVRUN_MRAW2_INT 185 +#define CMDQ_EVENT_TG_OVRUN_MRAW3_INT 186 +#define CMDQ_EVENT_DMA_R1_ERROR_MRAW0_INT 187 +#define CMDQ_EVENT_DMA_R1_ERROR_MRAW1_INT 188 +#define CMDQ_EVENT_DMA_R1_ERROR_MRAW2_INT 189 +#define CMDQ_EVENT_DMA_R1_ERROR_MRAW3_INT 190 +#define CMDQ_EVENT_PDA0_IRQO_EVENT_DONE_D1 191 +#define CMDQ_EVENT_PDA1_IRQO_EVENT_DONE_D1 192 +#define CMDQ_EVENT_CAM_SUBA_TG_INT1 193 +#define CMDQ_EVENT_CAM_SUBA_TG_INT2 194 +#define CMDQ_EVENT_CAM_SUBA_TG_INT3 195 +#define CMDQ_EVENT_CAM_SUBA_TG_INT4 196 +#define CMDQ_EVENT_CAM_SUBB_TG_INT1 197 +#define CMDQ_EVENT_CAM_SUBB_TG_INT2 198 +#define CMDQ_EVENT_CAM_SUBB_TG_INT3 199 +#define CMDQ_EVENT_CAM_SUBB_TG_INT4 200 +#define CMDQ_EVENT_CAM_SUBC_TG_INT1 201 +#define CMDQ_EVENT_CAM_SUBC_TG_INT2 202 +#define CMDQ_EVENT_CAM_SUBC_TG_INT3 203 +#define CMDQ_EVENT_CAM_SUBC_TG_INT4 204 +#define CMDQ_EVENT_CAM_SUBA_IMGO_R1_LOW_LATENCY_LINE_CNT_INT 205 +#define CMDQ_EVENT_CAM_SUBA_YUVO_R1_LOW_LATENCY_LINE_CNT_INT 206 +#define CMDQ_EVENT_CAM_SUBA_YUVO_R3_LOW_LATENCY_LINE_CNT_INT 207 +#define CMDQ_EVENT_CAM_SUBA_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT 208 +#define CMDQ_EVENT_CAM_SUBB_IMGO_R1_LOW_LATENCY_LINE_CNT_INT 209 +#define CMDQ_EVENT_CAM_SUBB_YUVO_R1_LOW_LATENCY_LINE_CNT_INT 210 +#define CMDQ_EVENT_CAM_SUBB_YUVO_R3_LOW_LATENCY_LINE_CNT_INT 211 +#define CMDQ_EVENT_CAM_SUBB_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT 212 +#define CMDQ_EVENT_CAM_SUBC_IMGO_R1_LOW_LATENCY_LINE_CNT_INT 213 +#define CMDQ_EVENT_CAM_SUBC_YUVO_R1_LOW_LATENCY_LINE_CNT_INT 214 +#define CMDQ_EVENT_CAM_SUBC_YUVO_R3_LOW_LATENCY_LINE_CNT_INT 215 +#define CMDQ_EVENT_CAM_SUBC_DRZS4NO_R1_LOW_LATENCY_LINE_CNT_INT 216 +#define CMDQ_EVENT_RAW_SEL_SOF_SUBA 217 +#define CMDQ_EVENT_RAW_SEL_SOF_SUBB 218 +#define CMDQ_EVENT_RAW_SEL_SOF_SUBC 219 +#define CMDQ_EVENT_CAM_SUBA_RING_BUFFER_OVERFLOW_INT_IN 220 +#define CMDQ_EVENT_CAM_SUBB_RING_BUFFER_OVERFLOW_INT_IN 221 +#define CMDQ_EVENT_CAM_SUBC_RING_BUFFER_OVERFLOW_INT_IN 222 +#define CMDQ_EVENT_VPP0_MDP_RDMA_SOF 256 +#define CMDQ_EVENT_VPP0_MDP_FG_SOF 257 +#define CMDQ_EVENT_VPP0_STITCH_SOF 258 +#define CMDQ_EVENT_VPP0_MDP_HDR_SOF 259 +#define CMDQ_EVENT_VPP0_MDP_AAL_SOF 260 +#define CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF 261 +#define CMDQ_EVENT_VPP0_MDP_TDSHP_SOF 262 +#define CMDQ_EVENT_VPP0_DISP_COLOR_SOF 263 +#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_SOF 264 +#define CMDQ_EVENT_VPP0_VPP_PADDING_IN_PADDING_SOF 265 +#define CMDQ_EVENT_VPP0_MDP_TCC_IN_SOF 266 +#define CMDQ_EVENT_VPP0_MDP_WROT_SOF 267 +#define CMDQ_EVENT_VPP0_WARP0_MMSYS_TOP_RELAY_SOF_PRE 269 +#define CMDQ_EVENT_VPP0_WARP1_MMSYS_TOP_RELAY_SOF_PRE 270 +#define CMDQ_EVENT_VPP0_VPP1_MMSYS_TOP_RELAY_SOF 271 +#define CMDQ_EVENT_VPP0_VPP1_IN_MMSYS_TOP_RELAY_SOF_PRE 272 +#define CMDQ_EVENT_VPP0_DISP_RDMA_SOF 273 +#define CMDQ_EVENT_VPP0_DISP_WDMA_SOF 274 +#define CMDQ_EVENT_VPP0_MDP_HMS_SOF 275 +#define CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE 288 +#define CMDQ_EVENT_VPP0_MDP_FG_TILE_DONE 289 +#define CMDQ_EVENT_VPP0_STITCH_FRAME_DONE 290 +#define CMDQ_EVENT_VPP0_MDP_HDR_FRAME_DONE 291 +#define CMDQ_EVENT_VPP0_MDP_AAL_FRAME_DONE 292 +#define CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE 293 +#define CMDQ_EVENT_VPP0_MDP_TDSHP_FRAME_DONE 294 +#define CMDQ_EVENT_VPP0_DISP_COLOR_FRAME_DONE 295 +#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_FRAME_DONE 296 +#define CMDQ_EVENT_VPP0_VPP_PADDING_IN_PADDING_FRAME_DONE 297 +#define CMDQ_EVENT_VPP0_MDP_TCC_TCC_FRAME_DONE 298 +#define CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE 299 +#define CMDQ_EVENT_VPP0_DISP_RDMA_FRAME_DONE 305 +#define CMDQ_EVENT_VPP0_DISP_WDMA_FRAME_DONE 306 +#define CMDQ_EVENT_VPP0_MDP_HMS_FRAME_DONE 307 +#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_0 320 +#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_1 321 +#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_2 322 +#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_3 323 +#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_4 324 +#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_5 325 +#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_6 326 +#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_7 327 +#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_8 328 +#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_9 329 +#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_10 330 +#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_11 331 +#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_12 332 +#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_13 333 +#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_14 334 +#define CMDQ_EVENT_VPP0_DISP_MUTEX_STREAM_DONE_15 335 +#define CMDQ_EVENT_VPP0_DISP_RDMA_0_UNDERRUN 336 +#define CMDQ_EVENT_VPP0_DISP_RDMA_1_UNDERRUN 337 +#define CMDQ_EVENT_VPP0_U_MERGE4_UNDERRUN 338 +#define CMDQ_EVENT_VPP0_U_VPP_SPLIT_VIDEO_0_OVERFLOW 339 +#define CMDQ_EVENT_VPP0_U_VPP_SPLIT_VIDEO_1_OVERFLOW 340 +#define CMDQ_EVENT_VPP0_DSI_0_UNDERRUN 341 +#define CMDQ_EVENT_VPP0_DSI_1_UNDERRUN 342 +#define CMDQ_EVENT_VPP0_DP_INTF_0 343 +#define CMDQ_EVENT_VPP0_DP_INTF_1 344 +#define CMDQ_EVENT_VPP0_DPI_0 345 +#define CMDQ_EVENT_VPP0_DPI_1 346 +#define CMDQ_EVENT_VPP0_MDP_RDMA_SW_RST_DONE 352 +#define CMDQ_EVENT_VPP0_MDP_RDMA_PM_VALID_EVENT 353 +#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_FRAME_RESET_DONE_PULSE 354 +#define CMDQ_EVENT_VPP0_MDP_WROT_SW_RST_DONE 355 +#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_0 356 +#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_1 357 +#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_2 358 +#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_3 359 +#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_4 360 +#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_5 361 +#define CMDQ_EVENT_VPP0_DISP_OVL_NOAFBC_TARGET_MATCH_6 362 +#define CMDQ_EVENT_VPP0_DISP_RDMA_DISP_RDMA_VALID_EVENT 363 +#define CMDQ_EVENT_VPP0_DISP_RDMA_DISP_RDMA_TARGET_LINE_EVENT 364 +#define CMDQ_EVENT_VPP0_DISP_WDMA_SW_RST_DONE 365 +#define CMDQ_EVENT_VPP0_DISP_WDMA_WDMA_VALID_EVENT 366 +#define CMDQ_EVENT_VPP0_DISP_WDMA_WDMA_TARGET_LINE_EVENT 367 +#define CMDQ_EVENT_VPP1_HDMI_META_SOF 384 +#define CMDQ_EVENT_VPP1_DGI_SOF 385 +#define CMDQ_EVENT_VPP1_VPP_SPLIT_SOF 386 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_TCC_SOF 387 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF 388 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF 389 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF 390 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_FG_SOF 391 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_FG_SOF 392 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_FG_SOF 393 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_HDR_SOF 394 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_HDR_SOF 395 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_HDR_SOF 396 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_AAL_SOF 397 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_AAL_SOF 398 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_AAL_SOF 399 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF 400 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF 401 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF 402 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_TDSHP_SOF 403 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_TDSHP_SOF 404 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_TDSHP_SOF 405 +#define CMDQ_EVENT_VPP1_SVPP2_VPP_MERGE_SOF 406 +#define CMDQ_EVENT_VPP1_SVPP3_VPP_MERGE_SOF 407 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_COLOR_SOF 408 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_COLOR_SOF 409 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_COLOR_SOF 410 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_OVL_SOF 411 +#define CMDQ_EVENT_VPP1_SVPP1_VPP_PAD_SOF 412 +#define CMDQ_EVENT_VPP1_SVPP2_VPP_PAD_SOF 413 +#define CMDQ_EVENT_VPP1_SVPP3_VPP_PAD_SOF 414 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF 415 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF 416 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF 417 +#define CMDQ_EVENT_VPP1_VPP0_DL_IRLY_SOF 418 +#define CMDQ_EVENT_VPP1_VPP0_DL_ORLY_SOF 419 +#define CMDQ_EVENT_VPP1_VDO0_DL_ORLY_0_SOF 420 +#define CMDQ_EVENT_VPP1_VDO0_DL_ORLY_1_SOF 421 +#define CMDQ_EVENT_VPP1_VDO1_DL_ORLY_0_SOF 422 +#define CMDQ_EVENT_VPP1_VDO1_DL_ORLY_1_SOF 423 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_FRAME_DONE 424 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE 425 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE 426 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE 427 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE 428 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE 429 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_OVL_FRAME_DONE 430 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_FRAME_DONE 431 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE 432 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE 433 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_FG_TILE_DONE 434 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_FG_TILE_DONE 435 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_FG_TILE_DONE 436 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_HDR_FRAME_DONE 437 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_HDR_FRAME_DONE 438 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_HDR_FRAME_DONE 439 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_AAL_FRAME_DONE 440 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_AAL_FRAME_DONE 441 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_AAL_FRAME_DONE 442 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_TDSHP_FRAME_DONE 443 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_TDSHP_FRAME_DONE 444 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_TDSHP_FRAME_DONE 445 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_COLOR_FRAME_DONE 446 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_COLOR_FRAME_DONE 447 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_COLOR_FRAME_DONE 448 +#define CMDQ_EVENT_VPP1_SVPP1_VPP_PAD_FRAME_DONE 449 +#define CMDQ_EVENT_VPP1_SVPP2_VPP_PAD_FRAME_DONE 450 +#define CMDQ_EVENT_VPP1_SVPP3_VPP_PAD_FRAME_DONE 451 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_TCC_FRAME_DONE 452 +#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_0 456 +#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_1 457 +#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_2 458 +#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_3 459 +#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_4 460 +#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_5 461 +#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_6 462 +#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_7 463 +#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_8 464 +#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_9 465 +#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_10 466 +#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_11 467 +#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_12 468 +#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_13 469 +#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_14 470 +#define CMDQ_EVENT_VPP1_MUTEX_STREAM_DONE_GCE_EVENT_15 471 +#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_0 472 +#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_1 473 +#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_2 474 +#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_3 475 +#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_4 476 +#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_5 477 +#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_6 478 +#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_7 479 +#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_8 480 +#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_9 481 +#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_10 482 +#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_11 483 +#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_12 484 +#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_13 485 +#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_14 486 +#define CMDQ_EVENT_VPP1_MUTEX_BUF_UNDERRUN_GCE_EVENT_15 487 +#define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_0 488 +#define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_1 489 +#define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_2 490 +#define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_3 491 +#define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_4 492 +#define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_5 493 +#define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_6 494 +#define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_7 495 +#define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_8 496 +#define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_9 497 +#define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_10 498 +#define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_11 499 +#define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_12 500 +#define CMDQ_EVENT_VPP1_DGI_SYNC_EVENT_13 501 +#define CMDQ_EVENT_VPP1_SVPP3_VPP_MERGE_GCE_EVENT 502 +#define CMDQ_EVENT_VPP1_SVPP2_VPP_MERGE_GCE_EVENT 503 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_OVL_GCE_EVENT 504 +#define CMDQ_EVENT_VPP1_VPP_SPLIT_DGI_GCE_EVENT 505 +#define CMDQ_EVENT_VPP1_VPP_SPLIT_HDMI_GCE_EVENT 506 +#define CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SW_RST_DONE_GCE_EVENT 507 +#define CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SW_RST_DONE_GCE_EVENT 508 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SW_RST_DONE_GCE_EVENT 509 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_OVL_NEW_EVENT_0 510 +#define CMDQ_EVENT_VPP1_SVPP1_MDP_OVL_NEW_EVENT_1 511 +#define CMDQ_EVENT_VDO0_DISP_OVL0_SOF 512 +#define CMDQ_EVENT_VDO0_DISP_WDMA0_SOF 513 +#define CMDQ_EVENT_VDO0_DISP_RDMA0_SOF 514 +#define CMDQ_EVENT_VDO0_DISP_COLOR0_SOF 515 +#define CMDQ_EVENT_VDO0_DISP_CCORR0_SOF 516 +#define CMDQ_EVENT_VDO0_DISP_AAL0_SOF 517 +#define CMDQ_EVENT_VDO0_DISP_GAMMA0_SOF 518 +#define CMDQ_EVENT_VDO0_DISP_DITHER0_SOF 519 +#define CMDQ_EVENT_VDO0_DSI0_SOF 520 +#define CMDQ_EVENT_VDO0_DSC_WRAP0C0_SOF 521 +#define CMDQ_EVENT_VDO0_DISP_OVL1_SOF 522 +#define CMDQ_EVENT_VDO0_DISP_WDMA1_SOF 523 +#define CMDQ_EVENT_VDO0_DISP_RDMA1_SOF 524 +#define CMDQ_EVENT_VDO0_DISP_COLOR1_SOF 525 +#define CMDQ_EVENT_VDO0_DISP_CCORR1_SOF 526 +#define CMDQ_EVENT_VDO0_DISP_AAL1_SOF 527 +#define CMDQ_EVENT_VDO0_DISP_GAMMA1_SOF 528 +#define CMDQ_EVENT_VDO0_DISP_DITHER1_SOF 529 +#define CMDQ_EVENT_VDO0_DSI1_SOF 530 +#define CMDQ_EVENT_VDO0_DSC_WRAP0C1_SOF 531 +#define CMDQ_EVENT_VDO0_VPP_MERGE0_SOF 532 +#define CMDQ_EVENT_VDO0_DP_INTF0_SOF 533 +#define CMDQ_EVENT_VDO0_DISP_DPI0_SOF 534 +#define CMDQ_EVENT_VDO0_DISP_DPI1_SOF 535 +#define CMDQ_EVENT_VDO0_DISP_POSTMASK0_SOF 536 +#define CMDQ_EVENT_VDO0_MDP_WROT0_SOF 537 +#define CMDQ_EVENT_VDO0_DISP_RSZ0_SOF 538 +#define CMDQ_EVENT_VDO0_VPP1_DL_RELAY0_SOF 539 +#define CMDQ_EVENT_VDO0_VPP1_DL_RELAY1_SOF 540 +#define CMDQ_EVENT_VDO0_VDO1_DL_RELAY2_SOF 541 +#define CMDQ_EVENT_VDO0_VDO0_DL_RELAY3_SOF 542 +#define CMDQ_EVENT_VDO0_VDO0_DL_RELAY4_SOF 543 +#define CMDQ_EVENT_VDO0_DISP_PWM0_SOF 544 +#define CMDQ_EVENT_VDO0_DISP_PWM1_SOF 545 +#define CMDQ_EVENT_VDO0_DISP_OVL0_O_FRAME_DONE 546 +#define CMDQ_EVENT_VDO0_DISP_WDMA0_FRAME_DONE 547 +#define CMDQ_EVENT_VDO0_DISP_RDMA0_FRAME_DONE 548 +#define CMDQ_EVENT_VDO0_DISP_COLOR0_O_FRAME_DONE 549 +#define CMDQ_EVENT_VDO0_DISP_CCORR0_O_FRAME_DONE 550 +#define CMDQ_EVENT_VDO0_DISP_AAL0_O_FRAME_DONE 551 +#define CMDQ_EVENT_VDO0_DISP_GAMMA0_O_FRAME_DONE 552 +#define CMDQ_EVENT_VDO0_DISP_DITHER0_O_FRAME_DONE 553 +#define CMDQ_EVENT_VDO0_DSI0_FRAME_DONE 554 +#define CMDQ_EVENT_VDO0_DSC_WRAP0_O_FRAME_DONE_0 555 +#define CMDQ_EVENT_VDO0_DISP_OVL1_O_FRAME_DONE 556 +#define CMDQ_EVENT_VDO0_DISP_WDMA1_O_FRAME_DONE 557 +#define CMDQ_EVENT_VDO0_DISP_RDMA1_O_FRAME_DONE 558 +#define CMDQ_EVENT_VDO0_DISP_COLOR1_O_FRAME_DONE 559 +#define CMDQ_EVENT_VDO0_DISP_CCORR1_O_FRAME_DONE 560 +#define CMDQ_EVENT_VDO0_DISP_AAL1_O_FRAME_DONE 561 +#define CMDQ_EVENT_VDO0_DISP_GAMMA1_O_FRAME_DONE 562 +#define CMDQ_EVENT_VDO0_DISP_DITHER1_O_FRAME_DONE 563 +#define CMDQ_EVENT_VDO0_DSI1_FRAME_DONE 564 +#define CMDQ_EVENT_VDO0_DSC_WRAP0_O_FRAME_DONE_1 565 +#define CMDQ_EVENT_VDO0_DP_INTF0_FRAME_DONE 567 +#define CMDQ_EVENT_VDO0_DISP_DPI0_O_FRAME_DONE 568 +#define CMDQ_EVENT_VDO0_DISP_DPI1_O_FRAME_DONE 569 +#define CMDQ_EVENT_VDO0_DISP_POSTMASK0_O_FRAME_DONE 570 +#define CMDQ_EVENT_VDO0_MDP_WROT0_O_FRAME_DONE 571 +#define CMDQ_EVENT_VDO0_DISP_RSZ0_O_FRAME_DONE 572 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0 574 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_1 575 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_2 576 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_3 577 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_4 578 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_5 579 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_6 580 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_7 581 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_8 582 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_9 583 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_10 584 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_11 585 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_12 586 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_13 587 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_14 588 +#define CMDQ_EVENT_VDO0_DISP_STREAM_DONE_15 589 +#define CMDQ_EVENT_VDO0_DISP_RDMA_0_UNDERRUN 590 +#define CMDQ_EVENT_VDO0_DISP_RDMA_1_UNDERRUN 591 +#define CMDQ_EVENT_VDO0_U_MERGE4_UNDERRUN 592 +#define CMDQ_EVENT_VDO0_DSI_0_UNDERRUN 595 +#define CMDQ_EVENT_VDO0_DSI_1_UNDERRUN 596 +#define CMDQ_EVENT_VDO0_DP_INTF_0 597 +#define CMDQ_EVENT_VDO0_DP_INTF_1 598 +#define CMDQ_EVENT_VDO0_DPI_0 599 +#define CMDQ_EVENT_VDO0_DPI_1 600 +#define CMDQ_EVENT_VDO0_DISP_SMIASSERT_ENG_EVENT 606 +#define CMDQ_EVENT_VDO0_DSI0_O_DSI_IRQ_EVENT_MM 607 +#define CMDQ_EVENT_VDO0_DSI0_TE_ENG_EVENT_MM 608 +#define CMDQ_EVENT_VDO0_DSI0_O_DSI_DONE_EVENT_MM 609 +#define CMDQ_EVENT_VDO0_DSI0_O_DSI_VACTL_EVENT_MM 610 +#define CMDQ_EVENT_VDO0_DSI1_O_DSI_IRQ_EVENT_MM 611 +#define CMDQ_EVENT_VDO0_DSI1_TE_ENG_EVENT_MM 612 +#define CMDQ_EVENT_VDO0_DSI1_O_DSI_DONE_EVENT_MM 613 +#define CMDQ_EVENT_VDO0_DSI1_O_DSI_VACTL_EVENT_MM 614 +#define CMDQ_EVENT_VDO0_DP_INTF0_O_DP_VSYNC_START_EVENT_MM 615 +#define CMDQ_EVENT_VDO0_DP_INTF0_O_DP_VSYNC_END_EVENT_MM 616 +#define CMDQ_EVENT_VDO0_DP_INTF0_O_DP_VDE_START_EVENT_MM 617 +#define CMDQ_EVENT_VDO0_DP_INTF0_O_DP_VDE_END_EVENT_MM 618 +#define CMDQ_EVENT_VDO0_DP_INTF0_O_VACT_TARGET_LINE_EVENT_MM 619 +#define CMDQ_EVENT_VDO0_DP_INTF0_O_LAST_SAFE_BLANK_EVENT_MM 620 +#define CMDQ_EVENT_VDO0_DP_INTF0_O_LAST_LINE_EVENT_MM 621 +#define CMDQ_EVENT_VDO0_DP_INTF0_O_TRIGGER_LOOP_CLEAR_EVENT_MM 622 +#define CMDQ_EVENT_VDO0_DP_INTF0_O_TARGET_LINE_0_EVENT_MM 623 +#define CMDQ_EVENT_VDO0_DP_INTF0_O_TARGET_LINE_1_EVENT_MM 624 +#define CMDQ_EVENT_VDO0_DISP_POSTMASK0_O_FRAME_RESET_DONE_PULSE 625 +#define CMDQ_EVENT_VDO0_VPP_MERGE0_O_VPP_MERGE_EVENT 626 +#define CMDQ_EVENT_VDO0_DISP_OVL0_O_FRAME_RESET_DONE_PULSE 627 +#define CMDQ_EVENT_VDO0_DISP_RDMA0_O_DISP_RDMA_TARGET_LINE_EVENT 628 +#define CMDQ_EVENT_VDO0_DISP_WDMA0_O_WDMA_TARGET_LINE_EVENT 629 +#define CMDQ_EVENT_VDO0_DISP_WDMA0_O_SW_RST_DONE 630 +#define CMDQ_EVENT_VDO0_DISP_OVL0_O_TARGET_MATCH_EVENT_0 631 +#define CMDQ_EVENT_VDO0_DISP_OVL0_O_TARGET_MATCH_EVENT_1 632 +#define CMDQ_EVENT_VDO0_DISP_OVL0_O_TARGET_MATCH_EVENT_2 633 +#define CMDQ_EVENT_VDO0_DISP_OVL0_O_TARGET_MATCH_EVENT_3 634 +#define CMDQ_EVENT_VDO0_DISP_OVL0_O_TARGET_MATCH_EVENT_4 635 +#define CMDQ_EVENT_VDO0_DISP_OVL0_O_TARGET_MATCH_EVENT_5 636 +#define CMDQ_EVENT_VDO0_DISP_OVL0_O_TARGET_MATCH_EVENT_6 637 +#define CMDQ_EVENT_VDO0_MDP_WROT0_O_SW_RST_DONE 638 +#define CMDQ_EVENT_VDO0_RESERVED 639 +#define CMDQ_EVENT_VDO1_MDP_RDMA0_SOF 640 +#define CMDQ_EVENT_VDO1_MDP_RDMA1_SOF 641 +#define CMDQ_EVENT_VDO1_MDP_RDMA2_SOF 642 +#define CMDQ_EVENT_VDO1_MDP_RDMA3_SOF 643 +#define CMDQ_EVENT_VDO1_MDP_RDMA4_SOF 644 +#define CMDQ_EVENT_VDO1_MDP_RDMA5_SOF 645 +#define CMDQ_EVENT_VDO1_MDP_RDMA6_SOF 646 +#define CMDQ_EVENT_VDO1_MDP_RDMA7_SOF 647 +#define CMDQ_EVENT_VDO1_DISP_PADDING0_SOF 648 +#define CMDQ_EVENT_VDO1_DISP_PADDING1_SOF 649 +#define CMDQ_EVENT_VDO1_DISP_PADDING2_SOF 650 +#define CMDQ_EVENT_VDO1_DISP_PADDING3_SOF 651 +#define CMDQ_EVENT_VDO1_DISP_PADDING4_SOF 652 +#define CMDQ_EVENT_VDO1_DISP_PADDING5_SOF 653 +#define CMDQ_EVENT_VDO1_DISP_PADDING6_SOF 654 +#define CMDQ_EVENT_VDO1_DISP_PADDING7_SOF 655 +#define CMDQ_EVENT_VDO1_DISP_RSZ0_SOF 656 +#define CMDQ_EVENT_VDO1_DISP_RSZ1_SOF 657 +#define CMDQ_EVENT_VDO1_DISP_RSZ2_SOF 658 +#define CMDQ_EVENT_VDO1_DISP_RSZ3_SOF 659 +#define CMDQ_EVENT_VDO1_VPP_MERGE0_SOF 660 +#define CMDQ_EVENT_VDO1_VPP_MERGE1_SOF 661 +#define CMDQ_EVENT_VDO1_VPP_MERGE2_SOF 662 +#define CMDQ_EVENT_VDO1_VPP_MERGE3_SOF 663 +#define CMDQ_EVENT_VDO1_VPP_MERGE4_SOF 664 +#define CMDQ_EVENT_VDO1_VPP2_DL_RELAY_SOF 665 +#define CMDQ_EVENT_VDO1_VPP3_DL_RELAY_SOF 666 +#define CMDQ_EVENT_VDO0_DSC_DL_ASYNC_SOF 667 +#define CMDQ_EVENT_VDO0_MERGE_DL_ASYNC_SOF 668 +#define CMDQ_EVENT_VDO1_OUT_DL_RELAY_SOF 669 +#define CMDQ_EVENT_VDO1_DISP_MIXER_SOF 670 +#define CMDQ_EVENT_VDO1_HDR_VDO_FE0_SOF 671 +#define CMDQ_EVENT_VDO1_HDR_VDO_FE1_SOF 672 +#define CMDQ_EVENT_VDO1_HDR_GFX_FE0_SOF 673 +#define CMDQ_EVENT_VDO1_HDR_GFX_FE1_SOF 674 +#define CMDQ_EVENT_VDO1_HDR_VDO_BE0_SOF 675 +#define CMDQ_EVENT_VDO1_HDR_MLOAD_SOF 676 +#define CMDQ_EVENT_VDO1_DPI0_EXT_SOF 677 +#define CMDQ_EVENT_VDO1_DPI1_EXT_SOF 678 +#define CMDQ_EVENT_VDO1_DP_INTF_EXT_EXT_SOF 679 +#define CMDQ_EVENT_VDO1_MDP_RDMA0_FRAME_DONE 680 +#define CMDQ_EVENT_VDO1_MDP_RDMA1_FRAME_DONE 681 +#define CMDQ_EVENT_VDO1_MDP_RDMA2_FRAME_DONE 682 +#define CMDQ_EVENT_VDO1_MDP_RDMA3_FRAME_DONE 683 +#define CMDQ_EVENT_VDO1_MDP_RDMA4_FRAME_DONE 684 +#define CMDQ_EVENT_VDO1_MDP_RDMA5_FRAME_DONE 685 +#define CMDQ_EVENT_VDO1_MDP_RDMA6_FRAME_DONE 686 +#define CMDQ_EVENT_VDO1_MDP_RDMA7_FRAME_DONE 687 +#define CMDQ_EVENT_VDO1_DISP_PADDING0_FRAME_DONE 688 +#define CMDQ_EVENT_VDO1_DISP_PADDING1_FRAME_DONE 689 +#define CMDQ_EVENT_VDO1_DISP_PADDING2_FRAME_DONE 690 +#define CMDQ_EVENT_VDO1_DISP_PADDING3_FRAME_DONE 691 +#define CMDQ_EVENT_VDO1_DISP_PADDING4_FRAME_DONE 692 +#define CMDQ_EVENT_VDO1_DISP_PADDING5_FRAME_DONE 693 +#define CMDQ_EVENT_VDO1_DISP_PADDING6_FRAME_DONE 694 +#define CMDQ_EVENT_VDO1_DISP_PADDING7_FRAME_DONE 695 +#define CMDQ_EVENT_VDO1_DISP_RSZ0_FRAME_DONE 696 +#define CMDQ_EVENT_VDO1_DISP_RSZ1_FRAME_DONE 697 +#define CMDQ_EVENT_VDO1_DISP_RSZ2_FRAME_DONE 698 +#define CMDQ_EVENT_VDO1_DISP_RSZ3_FRAME_DONE 699 +#define CMDQ_EVENT_VDO1_VPP_MERGE0_FRAME_DONE 700 +#define CMDQ_EVENT_VDO1_VPP_MERGE1_FRAME_DONE 701 +#define CMDQ_EVENT_VDO1_VPP_MERGE2_FRAME_DONE 702 +#define CMDQ_EVENT_VDO1_VPP_MERGE3_FRAME_DONE 703 +#define CMDQ_EVENT_VDO1_VPP_MERGE4_FRAME_DONE 704 +#define CMDQ_EVENT_VDO1_DPI0_FRAME_DONE 705 +#define CMDQ_EVENT_VDO1_DPI1_FRAME_DONE 706 +#define CMDQ_EVENT_VDO1_DP_INTF0_FRAME_DONE 707 +#define CMDQ_EVENT_VDO1_DISP_MIXER_FRAME_DONE_MM 708 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0 709 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_1 710 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_2 711 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_3 712 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_4 713 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_5 714 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_6 715 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_7 716 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_8 717 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_9 718 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_10 719 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_11 720 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_12 721 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_13 722 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_14 723 +#define CMDQ_EVENT_VDO1_STREAM_DONE_ENG_15 724 +#define CMDQ_EVENT_VDO1_DISP_RDMA_0_UNDERRUN 725 +#define CMDQ_EVENT_VDO1_DISP_RDMA_1_UNDERRUN 726 +#define CMDQ_EVENT_VDO1_U_MERGE4_UNDERRUN 727 +#define CMDQ_EVENT_VDO1_U_VPP_SPLIT_VIDEO_0_OVERFLOW 728 +#define CMDQ_EVENT_VDO1_U_VPP_SPLIT_VIDEO_1_OVERFLOW 729 +#define CMDQ_EVENT_VDO1_DSI_0_UNDERRUN 730 +#define CMDQ_EVENT_VDO1_DSI_1_UNDERRUN 731 +#define CMDQ_EVENT_VDO1_DP_INTF_0 732 +#define CMDQ_EVENT_VDO1_DP_INTF_1 733 +#define CMDQ_EVENT_VDO1_DPI_0 734 +#define CMDQ_EVENT_VDO1_DPI_1 735 +#define CMDQ_EVENT_VDO1_MDP_RDMA0_SW_RST_DONE 741 +#define CMDQ_EVENT_VDO1_MDP_RDMA1_SW_RST_DONE 742 +#define CMDQ_EVENT_VDO1_MDP_RDMA2_SW_RST_DONE 743 +#define CMDQ_EVENT_VDO1_MDP_RDMA3_SW_RST_DONE 744 +#define CMDQ_EVENT_VDO1_MDP_RDMA4_SW_RST_DONE 745 +#define CMDQ_EVENT_VDO1_MDP_RDMA5_SW_RST_DONE 746 +#define CMDQ_EVENT_VDO1_MDP_RDMA6_SW_RST_DONE 747 +#define CMDQ_EVENT_VDO1_MDP_RDMA7_SW_RST_DONE 748 +#define CMDQ_EVENT_VDO1_DP0_VDE_END_ENG_EVENT_MM 749 +#define CMDQ_EVENT_VDO1_DP0_VDE_START_ENG_EVENT_MM 750 +#define CMDQ_EVENT_VDO1_DP0_VSYNC_END_ENG_EVENT_MM 751 +#define CMDQ_EVENT_VDO1_DP0_VSYNC_START_ENG_EVENT_MM 752 +#define CMDQ_EVENT_VDO1_DP0_TARGET_LINE_ENG_EVENT_MM 753 +#define CMDQ_EVENT_VDO1_VPP_MERGE0_EVENT 754 +#define CMDQ_EVENT_VDO1_VPP_MERGE1_EVENT 755 +#define CMDQ_EVENT_VDO1_VPP_MERGE2_EVENT 756 +#define CMDQ_EVENT_VDO1_VPP_MERGE3_EVENT 757 +#define CMDQ_EVENT_VDO1_VPP_MERGE4_EVENT 758 +#define CMDQ_EVENT_VDO1_HDMITX_EVENT 759 +#define CMDQ_EVENT_VDO1_HDR_VDO_BE0_ADL_TRIG_EVENT_MM 760 +#define CMDQ_EVENT_VDO1_HDR_GFX_FE1_THDR_ADL_TRIG_EVENT_MM 761 +#define CMDQ_EVENT_VDO1_HDR_GFX_FE1_DM_ADL_TRIG_EVENT_MM 762 +#define CMDQ_EVENT_VDO1_HDR_GFX_FE0_THDR_ADL_TRIG_EVENT_MM 763 +#define CMDQ_EVENT_VDO1_HDR_GFX_FE0_DM_ADL_TRIG_EVENT_MM 764 +#define CMDQ_EVENT_VDO1_HDR_VDO_FE1_ADL_TRIG_EVENT_MM 765 +#define CMDQ_EVENT_VDO1_HDR_VDO_FE1_AD0_TRIG_EVENT_MM 766 +#define CMDQ_EVENT_VDO1_DPI0_TARGET_LINE_1_EVENT_MM 767 +#define CMDQ_EVENT_HANDSHAKE_0 768 +#define CMDQ_EVENT_HANDSHAKE_1 769 +#define CMDQ_EVENT_HANDSHAKE_2 770 +#define CMDQ_EVENT_HANDSHAKE_3 771 +#define CMDQ_EVENT_HANDSHAKE_4 772 +#define CMDQ_EVENT_HANDSHAKE_5 773 +#define CMDQ_EVENT_HANDSHAKE_6 774 +#define CMDQ_EVENT_HANDSHAKE_7 775 +#define CMDQ_EVENT_HANDSHAKE_8 776 +#define CMDQ_EVENT_HANDSHAKE_9 777 +#define CMDQ_EVENT_HANDSHAKE_10 778 +#define CMDQ_EVENT_HANDSHAKE_11 779 +#define CMDQ_EVENT_HANDSHAKE_12 780 +#define CMDQ_EVENT_HANDSHAKE_13 781 +#define CMDQ_EVENT_HANDSHAKE_14 782 +#define CMDQ_EVENT_HANDSHAKE_15 783 +#define CMDQ_EVENT_VDEC_SOC_EVENT_0 800 +#define CMDQ_EVENT_VDEC_SOC_EVENT_1 801 +#define CMDQ_EVENT_VDEC_SOC_EVENT_2 802 +#define CMDQ_EVENT_VDEC_SOC_EVENT_3 803 +#define CMDQ_EVENT_VDEC_SOC_EVENT_4 804 +#define CMDQ_EVENT_VDEC_SOC_EVENT_5 805 +#define CMDQ_EVENT_VDEC_SOC_EVENT_6 806 +#define CMDQ_EVENT_VDEC_SOC_EVENT_7 807 +#define CMDQ_EVENT_VDEC_SOC_EVENT_8 808 +#define CMDQ_EVENT_VDEC_SOC_EVENT_9 809 +#define CMDQ_EVENT_VDEC_SOC_EVENT_10 810 +#define CMDQ_EVENT_VDEC_SOC_EVENT_11 811 +#define CMDQ_EVENT_VDEC_SOC_EVENT_12 812 +#define CMDQ_EVENT_VDEC_SOC_EVENT_13 813 +#define CMDQ_EVENT_VDEC_SOC_EVENT_14 814 +#define CMDQ_EVENT_VDEC_SOC_EVENT_15 815 +#define CMDQ_EVENT_VDEC_CORE0_EVENT_0 832 +#define CMDQ_EVENT_VDEC_CORE0_EVENT_1 833 +#define CMDQ_EVENT_VDEC_CORE0_EVENT_2 834 +#define CMDQ_EVENT_VDEC_CORE0_EVENT_3 835 +#define CMDQ_EVENT_VDEC_CORE0_EVENT_4 836 +#define CMDQ_EVENT_VDEC_CORE0_EVENT_5 837 +#define CMDQ_EVENT_VDEC_CORE0_EVENT_6 838 +#define CMDQ_EVENT_VDEC_CORE0_EVENT_7 839 +#define CMDQ_EVENT_VDEC_CORE0_EVENT_8 840 +#define CMDQ_EVENT_VDEC_CORE0_EVENT_9 841 +#define CMDQ_EVENT_VDEC_CORE0_EVENT_10 842 +#define CMDQ_EVENT_VDEC_CORE0_EVENT_11 843 +#define CMDQ_EVENT_VDEC_CORE0_EVENT_12 844 +#define CMDQ_EVENT_VDEC_CORE0_EVENT_13 845 +#define CMDQ_EVENT_VDEC_CORE0_EVENT_14 846 +#define CMDQ_EVENT_VDEC_CORE0_EVENT_15 847 +#define CMDQ_EVENT_VENC_TOP_VENC_FRAME_DONE 865 +#define CMDQ_EVENT_VENC_TOP_VENC_PAUSE_DONE 866 +#define CMDQ_EVENT_VENC_TOP_JPGENC_DONE 867 +#define CMDQ_EVENT_VENC_TOP_VENC_MB_DONE 868 +#define CMDQ_EVENT_VENC_TOP_VENC_128BYTE_DONE 869 +#define CMDQ_EVENT_VENC_TOP_JPGDEC_DONE 870 +#define CMDQ_EVENT_VENC_TOP_VENC_SLICE_DONE 871 +#define CMDQ_EVENT_VENC_TOP_JPGDEC_INSUFF_DONE 872 +#define CMDQ_EVENT_VENC_TOP_WP_2ND_STAGE_DONE 874 +#define CMDQ_EVENT_VENC_TOP_WP_3RD_STAGE_DONE 875 +#define CMDQ_EVENT_VENC_TOP_PPS_HEADER_DONE 876 +#define CMDQ_EVENT_VENC_TOP_SPS_HEADER_DONE 877 +#define CMDQ_EVENT_VENC_TOP_VPS_HEADER_DONE 878 +#define CMDQ_EVENT_WPE_VPP0_WPE_GCE_FRAME_DONE 882 +#define CMDQ_EVENT_WPE_VPP0_WPE_DONE_SYNC_OUT 883 +#define CMDQ_EVENT_SVPP1_MDP_OVL_NEW_EVENT_2 896 +#define CMDQ_EVENT_SVPP1_MDP_OVL_NEW_EVENT_3 897 +#define CMDQ_EVENT_SVPP1_MDP_OVL_NEW_EVENT_4 898 +#define CMDQ_EVENT_SVPP1_MDP_OVL_NEW_EVENT_5 899 +#define CMDQ_EVENT_SVPP1_MDP_OVL_NEW_EVENT_6 900 +#define CMDQ_EVENT_VDO1_DPI0_TARGET_LINE_0_EVENT_MM 928 +#define CMDQ_EVENT_VDO1_DPI0_TRIGGER_LOOP_CLEAR_EVENT_MM 929 +#define CMDQ_EVENT_VDO1_DPI0_LAST_LINE_EVENT_MM 930 +#define CMDQ_EVENT_VDO1_DPI0_LAST_SAFE_BLANK_EVENT_MM 931 +#define CMDQ_EVENT_VDO1_DPI0_VSYNC_START_EVENT_MM 932 +#define CMDQ_EVENT_VDO1_DPI1_TARGET_LINE_1_EVENT_MM 933 +#define CMDQ_EVENT_VDO1_DPI1_TARGET_LINE_0_EVENT_MM 934 +#define CMDQ_EVENT_VDO1_DPI1_TRIGGER_LOOP_CLEAR_EVENT_MM 935 +#define CMDQ_EVENT_VDO1_DPI1_LAST_LINE_EVENT_MM 936 +#define CMDQ_EVENT_VDO1_DPI1_LAST_SAFE_BLANK_EVENT_MM 937 +#define CMDQ_EVENT_VDO1_DPI1_VSYNC_START_EVENT_MM 938 +#define CMDQ_EVENT_VDO1_DP_INTF_TARGET_LINE_1_EVENT_MM 939 +#define CMDQ_EVENT_VDO1_DP_INTF_TARGET_LINE_0_EVENT_MM 940 +#define CMDQ_EVENT_VDO1_DP_INTF_TRIGGER_LOOP_CLEAR_EVENT_MM 941 +#define CMDQ_EVENT_VDO1_DP_INTF_LAST_LINE_EVENT_MM 942 +#define CMDQ_EVENT_VDO1_DP_INTF_LAST_SAFE_BLANK_EVENT_MM 943 +#define CMDQ_EVENT_VBLANK_FALLING 946 +#define CMDQ_EVENT_VSC_FINISH 947 +#define CMDQ_EVENT_TPR_0 962 +#define CMDQ_EVENT_TPR_1 963 +#define CMDQ_EVENT_TPR_2 964 +#define CMDQ_EVENT_TPR_3 965 +#define CMDQ_EVENT_TPR_4 966 +#define CMDQ_EVENT_TPR_5 967 +#define CMDQ_EVENT_TPR_6 968 +#define CMDQ_EVENT_TPR_7 969 +#define CMDQ_EVENT_TPR_8 970 +#define CMDQ_EVENT_TPR_9 971 +#define CMDQ_EVENT_TPR_10 972 +#define CMDQ_EVENT_TPR_11 973 +#define CMDQ_EVENT_TPR_12 974 +#define CMDQ_EVENT_TPR_13 975 +#define CMDQ_EVENT_TPR_14 976 +#define CMDQ_EVENT_TPR_15 977 +#define CMDQ_EVENT_TPR_16 978 +#define CMDQ_EVENT_TPR_17 979 +#define CMDQ_EVENT_TPR_18 980 +#define CMDQ_EVENT_TPR_19 981 +#define CMDQ_EVENT_TPR_20 982 +#define CMDQ_EVENT_TPR_21 983 +#define CMDQ_EVENT_TPR_22 984 +#define CMDQ_EVENT_TPR_23 985 +#define CMDQ_EVENT_TPR_24 986 +#define CMDQ_EVENT_TPR_25 987 +#define CMDQ_EVENT_TPR_26 988 +#define CMDQ_EVENT_TPR_27 989 +#define CMDQ_EVENT_TPR_28 990 +#define CMDQ_EVENT_TPR_29 991 +#define CMDQ_EVENT_TPR_30 992 +#define CMDQ_EVENT_TPR_31 993 +#define CMDQ_EVENT_TPR_TIMEOUT_0 994 +#define CMDQ_EVENT_TPR_TIMEOUT_1 995 +#define CMDQ_EVENT_TPR_TIMEOUT_2 996 +#define CMDQ_EVENT_TPR_TIMEOUT_3 997 +#define CMDQ_EVENT_TPR_TIMEOUT_4 998 +#define CMDQ_EVENT_TPR_TIMEOUT_5 999 +#define CMDQ_EVENT_TPR_TIMEOUT_6 1000 +#define CMDQ_EVENT_TPR_TIMEOUT_7 1001 +#define CMDQ_EVENT_TPR_TIMEOUT_8 1002 +#define CMDQ_EVENT_TPR_TIMEOUT_9 1003 +#define CMDQ_EVENT_TPR_TIMEOUT_10 1004 +#define CMDQ_EVENT_TPR_TIMEOUT_11 1005 +#define CMDQ_EVENT_TPR_TIMEOUT_12 1006 +#define CMDQ_EVENT_TPR_TIMEOUT_13 1007 +#define CMDQ_EVENT_TPR_TIMEOUT_14 1008 +#define CMDQ_EVENT_TPR_TIMEOUT_15 1009 +#define CMDQ_EVENT_OUTPIN_0 1018 +#define CMDQ_EVENT_OUTPIN_1 1019 + +#define CMDQ_SYNC_TOKEN_IMGSYS_WPE_EIS 124 +#define CMDQ_SYNC_TOKEN_IMGSYS_WPE_TNR 125 +#define CMDQ_SYNC_TOKEN_IMGSYS_WPE_LITE 126 +#define CMDQ_SYNC_TOKEN_IMGSYS_TRAW 127 +#define CMDQ_SYNC_TOKEN_IMGSYS_LTRAW 128 +#define CMDQ_SYNC_TOKEN_CAMSYS_POOL_1 223 +#define CMDQ_SYNC_TOKEN_CAMSYS_POOL_2 224 +#define CMDQ_SYNC_TOKEN_CAMSYS_POOL_3 225 +#define CMDQ_SYNC_TOKEN_CAMSYS_POOL_4 226 +#define CMDQ_SYNC_TOKEN_CAMSYS_POOL_5 227 +#define CMDQ_SYNC_TOKEN_CAMSYS_POOL_6 228 +#define CMDQ_SYNC_TOKEN_CAMSYS_POOL_7 229 +#define CMDQ_SYNC_TOKEN_CAMSYS_POOL_8 230 +#define CMDQ_SYNC_TOKEN_CAMSYS_POOL_9 231 +#define CMDQ_SYNC_TOKEN_CAMSYS_POOL_10 232 +#define CMDQ_SYNC_TOKEN_IMGSYS_XTRAW 233 +#define CMDQ_SYNC_TOKEN_IMGSYS_DIP 234 +#define CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_A 235 +#define CMDQ_SYNC_TOKEN_IMGSYS_PQDIP_B 236 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_1 237 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_2 238 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_3 239 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_4 240 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_5 241 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_6 242 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_7 243 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_8 244 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_9 245 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_10 246 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_11 247 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_12 248 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_13 249 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_14 250 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_15 251 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_16 252 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_17 253 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_18 254 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_19 255 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_20 276 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_21 277 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_22 278 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_23 279 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_24 280 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_25 281 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_26 282 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_27 283 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_28 284 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_29 285 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_30 286 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_31 287 +#define CMDQ_SYNC_TOKEN_IPESYS_ME 300 +#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_TRAW 301 +#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_LTRAW 302 +#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_XTRAW 303 +#define CMDQ_SYNC_TOKEN_IMGSYS_VSS_DIP 304 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_32 308 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_33 309 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_34 310 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_35 311 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_36 312 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_37 313 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_38 314 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_39 315 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_40 316 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_41 370 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_42 371 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_43 372 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_44 373 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_45 374 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_46 375 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_47 376 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_48 377 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_49 378 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_50 379 +#define CMDQ_SYNC_TOKEN_TZMP_ISP_WAIT 380 +#define CMDQ_SYNC_TOKEN_TZMP_ISP_SET 381 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_51 790 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_52 791 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_53 792 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_54 793 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_55 794 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_56 795 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_57 796 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_58 797 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_59 798 +#define CMDQ_SYNC_TOKEN_IMGSYS_POOL_60 799 +#define CMDQ_SYNC_TOKEN_PREBUILT_MDP_WAIT 816 +#define CMDQ_SYNC_TOKEN_PREBUILT_MDP_SET 817 +#define CMDQ_SYNC_TOKEN_PREBUILT_MDP_LOCK 818 +#define CMDQ_SYNC_TOKEN_PREBUILT_MML_WAIT 819 +#define CMDQ_SYNC_TOKEN_PREBUILT_MML_SET 820 +#define CMDQ_SYNC_TOKEN_PREBUILT_MML_LOCK 821 +#define CMDQ_SYNC_TOKEN_PREBUILT_VFMT_WAIT 822 +#define CMDQ_SYNC_TOKEN_PREBUILT_VFMT_SET 823 +#define CMDQ_SYNC_TOKEN_PREBUILT_VFMT_LOCK 824 +#define CMDQ_SYNC_TOKEN_PREBUILT_DISP_WAIT 825 +#define CMDQ_SYNC_TOKEN_PREBUILT_DISP_SET 826 +#define CMDQ_SYNC_TOKEN_PREBUILT_DISP_LOCK 827 +#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY 848 +#define CMDQ_SYNC_TOKEN_STREAM_EOF 849 +#define CMDQ_SYNC_TOKEN_ESD_EOF 850 +#define CMDQ_SYNC_TOKEN_STREAM_BLOCK 851 +#define CMDQ_SYNC_TOKEN_CABC_EOF 852 +#define CMDQ_SYNC_TOKEN_VENC_INPUT_READY 853 +#define CMDQ_SYNC_TOKEN_VENC_EOF 854 +#define CMDQ_SYNC_TOKEN_SECURE_THR_EOF 855 +#define CMDQ_SYNC_TOKEN_USER_0 856 +#define CMDQ_SYNC_TOKEN_USER_1 857 +#define CMDQ_SYNC_TOKEN_POLL_MONITOR 858 +#define CMDQ_TOKEN_TPR_LOCK 859 +#define CMDQ_SYNC_TOKEN_MSS 860 +#define CMDQ_SYNC_TOKEN_MSF 861 +#define CMDQ_SYNC_TOKEN_GPR_SET_0 884 +#define CMDQ_SYNC_TOKEN_GPR_SET_1 885 +#define CMDQ_SYNC_TOKEN_GPR_SET_2 886 +#define CMDQ_SYNC_TOKEN_GPR_SET_3 887 +#define CMDQ_SYNC_TOKEN_GPR_SET_4 888 +#define CMDQ_SYNC_RESOURCE_WROT0 889 +#define CMDQ_SYNC_RESOURCE_WROT1 890 +#define CMDQ_SYNC_TOKEN_DISP_VA_START 1012 +#define CMDQ_SYNC_TOKEN_DISP_VA_END 1013 + +#endif -- cgit v1.2.3 From bed4a63ea4ae77cfe5aae004ef87379f0655260a Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Mon, 19 Dec 2022 20:07:52 +0100 Subject: netfilter: nf_tables: consolidate set description Add the following fields to the set description: - key type - data type - object type - policy - gc_int: garbage collection interval) - timeout: element timeout This prepares for stricter set type checks on updates in a follow up patch. Signed-off-by: Pablo Neira Ayuso --- include/net/netfilter/nf_tables.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'include') diff --git a/include/net/netfilter/nf_tables.h b/include/net/netfilter/nf_tables.h index e69ce23566ea..4957b4775757 100644 --- a/include/net/netfilter/nf_tables.h +++ b/include/net/netfilter/nf_tables.h @@ -312,17 +312,29 @@ struct nft_set_iter { /** * struct nft_set_desc - description of set elements * + * @ktype: key type * @klen: key length + * @dtype: data type * @dlen: data length + * @objtype: object type + * @flags: flags * @size: number of set elements + * @policy: set policy + * @gc_int: garbage collector interval * @field_len: length of each field in concatenation, bytes * @field_count: number of concatenated fields in element * @expr: set must support for expressions */ struct nft_set_desc { + u32 ktype; unsigned int klen; + u32 dtype; unsigned int dlen; + u32 objtype; unsigned int size; + u32 policy; + u32 gc_int; + u64 timeout; u8 field_len[NFT_REG32_COUNT]; u8 field_count; bool expr; -- cgit v1.2.3 From 123b99619cca94bdca0bf7bde9abe28f0a0dfe06 Mon Sep 17 00:00:00 2001 From: Pablo Neira Ayuso Date: Mon, 19 Dec 2022 20:10:12 +0100 Subject: netfilter: nf_tables: honor set timeout and garbage collection updates Set timeout and garbage collection interval updates are ignored on updates. Add transaction to update global set element timeout and garbage collection interval. Fixes: 96518518cc41 ("netfilter: add nftables") Suggested-by: Florian Westphal Signed-off-by: Pablo Neira Ayuso --- include/net/netfilter/nf_tables.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/net/netfilter/nf_tables.h b/include/net/netfilter/nf_tables.h index 4957b4775757..9430128aae99 100644 --- a/include/net/netfilter/nf_tables.h +++ b/include/net/netfilter/nf_tables.h @@ -597,7 +597,9 @@ void *nft_set_catchall_gc(const struct nft_set *set); static inline unsigned long nft_set_gc_interval(const struct nft_set *set) { - return set->gc_int ? msecs_to_jiffies(set->gc_int) : HZ; + u32 gc_int = READ_ONCE(set->gc_int); + + return gc_int ? msecs_to_jiffies(gc_int) : HZ; } /** @@ -1570,6 +1572,9 @@ struct nft_trans_rule { struct nft_trans_set { struct nft_set *set; u32 set_id; + u32 gc_int; + u64 timeout; + bool update; bool bound; }; @@ -1579,6 +1584,12 @@ struct nft_trans_set { (((struct nft_trans_set *)trans->data)->set_id) #define nft_trans_set_bound(trans) \ (((struct nft_trans_set *)trans->data)->bound) +#define nft_trans_set_update(trans) \ + (((struct nft_trans_set *)trans->data)->update) +#define nft_trans_set_timeout(trans) \ + (((struct nft_trans_set *)trans->data)->timeout) +#define nft_trans_set_gc_int(trans) \ + (((struct nft_trans_set *)trans->data)->gc_int) struct nft_trans_chain { bool update; -- cgit v1.2.3 From 00a734104af7d878f1252d49eff9298785c6cbdc Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 8 Dec 2022 10:42:05 -0600 Subject: ACPI: video: Allow GPU drivers to report no panels The current logic for the ACPI backlight detection will create a backlight device if no native or vendor drivers have created 8 seconds after the system has booted if the ACPI tables included backlight control methods. If the GPU drivers have loaded, they may be able to report whether any LCD panels were found. Allow using this information to factor in whether to enable the fallback logic for making an acpi_video0 backlight device. Suggested-by: Hans de Goede Signed-off-by: Mario Limonciello Reviewed-by: Hans de Goede Signed-off-by: Rafael J. Wysocki --- include/acpi/video.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/acpi/video.h b/include/acpi/video.h index a275c35e5249..8ed9bec03e53 100644 --- a/include/acpi/video.h +++ b/include/acpi/video.h @@ -53,6 +53,7 @@ enum acpi_backlight_type { }; #if IS_ENABLED(CONFIG_ACPI_VIDEO) +extern void acpi_video_report_nolcd(void); extern int acpi_video_register(void); extern void acpi_video_unregister(void); extern void acpi_video_register_backlight(void); @@ -69,6 +70,7 @@ extern int acpi_video_get_levels(struct acpi_device *device, struct acpi_video_device_brightness **dev_br, int *pmax_level); #else +static inline void acpi_video_report_nolcd(void) { return; }; static inline int acpi_video_register(void) { return -ENODEV; } static inline void acpi_video_unregister(void) { return; } static inline void acpi_video_register_backlight(void) { return; } -- cgit v1.2.3 From 7fac54b93ad13e5e7ac237af33eb2a0940eaeea0 Mon Sep 17 00:00:00 2001 From: Rong Tao Date: Wed, 21 Dec 2022 20:36:27 +0800 Subject: atm: uapi: fix spelling typos in comments Fix the typo of 'Unsuported' in atmbr2684.h Signed-off-by: Rong Tao Link: https://lore.kernel.org/r/tencent_F1354BEC925C65EA357E741E91DF2044E805@qq.com Signed-off-by: Jakub Kicinski --- include/uapi/linux/atmbr2684.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/uapi/linux/atmbr2684.h b/include/uapi/linux/atmbr2684.h index a9e2250cd720..d47c47d06f11 100644 --- a/include/uapi/linux/atmbr2684.h +++ b/include/uapi/linux/atmbr2684.h @@ -38,7 +38,7 @@ */ #define BR2684_ENCAPS_VC (0) /* VC-mux */ #define BR2684_ENCAPS_LLC (1) -#define BR2684_ENCAPS_AUTODETECT (2) /* Unsuported */ +#define BR2684_ENCAPS_AUTODETECT (2) /* Unsupported */ /* * Is this VC bridged or routed? -- cgit v1.2.3 From b0305c1e0e27ad91187bc6d5ac3d502799faf239 Mon Sep 17 00:00:00 2001 From: David Woodhouse Date: Mon, 26 Dec 2022 12:03:19 +0000 Subject: KVM: x86/xen: Add KVM_XEN_INVALID_GPA and KVM_XEN_INVALID_GFN to uapi These are (uint64_t)-1 magic values are a userspace ABI, allowing the shared info pages and other enlightenments to be disabled. This isn't a Xen ABI because Xen doesn't let the guest turn these off except with the full SHUTDOWN_soft_reset mechanism. Under KVM, the userspace VMM is expected to handle soft reset, and tear down the kernel parts of the enlightenments accordingly. Suggested-by: Sean Christopherson Signed-off-by: David Woodhouse Message-Id: <20221226120320.1125390-5-dwmw2@infradead.org> Signed-off-by: Paolo Bonzini --- include/uapi/linux/kvm.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 20522d4ba1e0..55155e262646 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -1767,6 +1767,7 @@ struct kvm_xen_hvm_attr { __u8 runstate_update_flag; struct { __u64 gfn; +#define KVM_XEN_INVALID_GFN ((__u64)-1) } shared_info; struct { __u32 send_port; @@ -1798,6 +1799,7 @@ struct kvm_xen_hvm_attr { } u; }; + /* Available with KVM_CAP_XEN_HVM / KVM_XEN_HVM_CONFIG_SHARED_INFO */ #define KVM_XEN_ATTR_TYPE_LONG_MODE 0x0 #define KVM_XEN_ATTR_TYPE_SHARED_INFO 0x1 @@ -1823,6 +1825,7 @@ struct kvm_xen_vcpu_attr { __u16 pad[3]; union { __u64 gpa; +#define KVM_XEN_INVALID_GPA ((__u64)-1) __u64 pad[8]; struct { __u64 state; -- cgit v1.2.3 From 9eb803402a2a83400c6c6afd900e3b7c87c06816 Mon Sep 17 00:00:00 2001 From: Stefan Metzmacher Date: Wed, 16 Nov 2022 21:25:24 +0100 Subject: uapi:io_uring.h: allow linux/time_types.h to be skipped include/uapi/linux/io_uring.h is synced 1:1 into liburing:src/include/liburing/io_uring.h. liburing has a configure check to detect the need for linux/time_types.h. It can opt-out by defining UAPI_LINUX_IO_URING_H_SKIP_LINUX_TIME_TYPES_H Fixes: 78a861b94959 ("io_uring: add sync cancelation API through io_uring_register()") Link: https://github.com/axboe/liburing/issues/708 Link: https://github.com/axboe/liburing/pull/709 Link: https://lore.kernel.org/io-uring/20221115212614.1308132-1-ammar.faizi@intel.com/T/#m9f5dd571cd4f6a5dee84452dbbca3b92ba7a4091 CC: Jens Axboe Cc: Ammar Faizi Signed-off-by: Stefan Metzmacher Reviewed-by: Ammar Faizi Link: https://lore.kernel.org/r/7071a0a1d751221538b20b63f9160094fc7e06f4.1668630247.git.metze@samba.org Signed-off-by: Jens Axboe --- include/uapi/linux/io_uring.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include') diff --git a/include/uapi/linux/io_uring.h b/include/uapi/linux/io_uring.h index 9d4c4078e8d0..2780bce62faf 100644 --- a/include/uapi/linux/io_uring.h +++ b/include/uapi/linux/io_uring.h @@ -10,7 +10,15 @@ #include #include +/* + * this file is shared with liburing and that has to autodetect + * if linux/time_types.h is available or not, it can + * define UAPI_LINUX_IO_URING_H_SKIP_LINUX_TIME_TYPES_H + * if linux/time_types.h is not available + */ +#ifndef UAPI_LINUX_IO_URING_H_SKIP_LINUX_TIME_TYPES_H #include +#endif #ifdef __cplusplus extern "C" { -- cgit v1.2.3 From 0e50d999903c009b6a9cd2277c82d6798d982e31 Mon Sep 17 00:00:00 2001 From: David Howells Date: Sat, 24 Dec 2022 14:49:00 +0000 Subject: rxrpc: Fix a couple of potential use-after-frees At the end of rxrpc_recvmsg(), if a call is found, the call is put and then a trace line is emitted referencing that call in a couple of places - but the call may have been deallocated by the time those traces happen. Fix this by stashing the call debug_id in a variable and passing that to the tracepoint rather than the call pointer. Fixes: 849979051cbc ("rxrpc: Add a tracepoint to follow what recvmsg does") Signed-off-by: David Howells cc: Marc Dionne cc: linux-afs@lists.infradead.org Signed-off-by: David S. Miller --- include/trace/events/rxrpc.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/trace/events/rxrpc.h b/include/trace/events/rxrpc.h index c6cfed00d0c6..5f9dd7389536 100644 --- a/include/trace/events/rxrpc.h +++ b/include/trace/events/rxrpc.h @@ -1062,10 +1062,10 @@ TRACE_EVENT(rxrpc_receive, ); TRACE_EVENT(rxrpc_recvmsg, - TP_PROTO(struct rxrpc_call *call, enum rxrpc_recvmsg_trace why, + TP_PROTO(unsigned int call_debug_id, enum rxrpc_recvmsg_trace why, int ret), - TP_ARGS(call, why, ret), + TP_ARGS(call_debug_id, why, ret), TP_STRUCT__entry( __field(unsigned int, call ) @@ -1074,7 +1074,7 @@ TRACE_EVENT(rxrpc_recvmsg, ), TP_fast_assign( - __entry->call = call ? call->debug_id : 0; + __entry->call = call_debug_id; __entry->why = why; __entry->ret = ret; ), -- cgit v1.2.3 From b9e05399d9273c8c066e73db1e6e85364003030c Mon Sep 17 00:00:00 2001 From: Si-Wei Liu Date: Mon, 10 Oct 2022 10:27:03 -0700 Subject: vdpa: merge functionally duplicated dev_features attributes We can merge VDPA_ATTR_VDPA_DEV_SUPPORTED_FEATURES with VDPA_ATTR_DEV_FEATURES which is functionally equivalent. While at it, tweak the comment in header file to make user provioned device features distinguished from those supported by the parent mgmtdev device: the former of which can be inherited as a whole from the latter, or can be a subset of the latter if explicitly specified. Signed-off-by: Si-Wei Liu Message-Id: <1665422823-18364-1-git-send-email-si-wei.liu@oracle.com> Signed-off-by: Michael S. Tsirkin Acked-by: Jason Wang --- include/uapi/linux/vdpa.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'include') diff --git a/include/uapi/linux/vdpa.h b/include/uapi/linux/vdpa.h index 9bd79235c875..54b649ab0f22 100644 --- a/include/uapi/linux/vdpa.h +++ b/include/uapi/linux/vdpa.h @@ -53,11 +53,9 @@ enum vdpa_attr { VDPA_ATTR_DEV_VENDOR_ATTR_NAME, /* string */ VDPA_ATTR_DEV_VENDOR_ATTR_VALUE, /* u64 */ + /* virtio features that are provisioned to the vDPA device */ VDPA_ATTR_DEV_FEATURES, /* u64 */ - /* virtio features that are supported by the vDPA device */ - VDPA_ATTR_VDPA_DEV_SUPPORTED_FEATURES, /* u64 */ - /* new attributes must be added above here */ VDPA_ATTR_MAX, }; -- cgit v1.2.3 From 40cab44b9089a41f71bbd0eff753eb91d5dafd68 Mon Sep 17 00:00:00 2001 From: Pedro Tammela Date: Tue, 27 Dec 2022 11:04:59 -0300 Subject: net/sched: fix retpoline wrapper compilation on configs without tc filters Rudi reports a compilation failure on x86_64 when CONFIG_NET_CLS or CONFIG_NET_CLS_ACT is not set but CONFIG_RETPOLINE is set. A misplaced '#endif' was causing the issue. Fixes: 7f0e810220e2 ("net/sched: add retpoline wrapper for tc") Tested-by: Rudi Heitbaum Signed-off-by: Pedro Tammela Signed-off-by: David S. Miller --- include/net/tc_wrapper.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/net/tc_wrapper.h b/include/net/tc_wrapper.h index ceed2fc089ff..d323fffb839a 100644 --- a/include/net/tc_wrapper.h +++ b/include/net/tc_wrapper.h @@ -216,6 +216,8 @@ skip: return tp->classify(skb, tp, res); } +#endif /* CONFIG_NET_CLS */ + static inline void tc_wrapper_init(void) { #ifdef CONFIG_X86 @@ -224,8 +226,6 @@ static inline void tc_wrapper_init(void) #endif } -#endif /* CONFIG_NET_CLS */ - #else #define TC_INDIRECT_SCOPE static -- cgit v1.2.3 From 685e6311637e46f3212439ce2789f8a300e5050f Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Wed, 21 Dec 2022 10:30:45 +0100 Subject: nvme: fix the NVME_CMD_EFFECTS_CSE_MASK definition 3 << 16 does not generate the correct mask for bits 16, 17 and 18. Use the GENMASK macro to generate the correct mask instead. Fixes: 84fef62d135b ("nvme: check admin passthru command effects") Signed-off-by: Christoph Hellwig Reviewed-by: Keith Busch Reviewed-by: Sagi Grimberg Reviewed-by: Kanchan Joshi --- include/linux/nvme.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/linux/nvme.h b/include/linux/nvme.h index d6be2a686100..d1cd53f2b6ab 100644 --- a/include/linux/nvme.h +++ b/include/linux/nvme.h @@ -7,6 +7,7 @@ #ifndef _LINUX_NVME_H #define _LINUX_NVME_H +#include #include #include @@ -639,7 +640,7 @@ enum { NVME_CMD_EFFECTS_NCC = 1 << 2, NVME_CMD_EFFECTS_NIC = 1 << 3, NVME_CMD_EFFECTS_CCC = 1 << 4, - NVME_CMD_EFFECTS_CSE_MASK = 3 << 16, + NVME_CMD_EFFECTS_CSE_MASK = GENMASK(18, 16), NVME_CMD_EFFECTS_UUID_SEL = 1 << 19, }; -- cgit v1.2.3 From 6f99ac04c469b5d0a180a4ccea99d25d5dc9d21c Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Tue, 13 Dec 2022 16:13:38 +0100 Subject: nvme: consult the CSE log page for unprivileged passthrough Commands like Write Zeros can change the contents of a namespaces without actually transferring data. To protect against this, check the Commands Supported and Effects log is supported by the controller for any unprivileg command passthrough and refuse unprivileged passthrough if the command has any effects that can change data or metadata. Note: While the Commands Support and Effects log page has only been mandatory since NVMe 2.0, it is widely supported because Windows requires it for any command passthrough from userspace. Fixes: e4fbcf32c860 ("nvme: identify-namespace without CAP_SYS_ADMIN") Signed-off-by: Christoph Hellwig Reviewed-by: Keith Busch Reviewed-by: Sagi Grimberg Reviewed-by: Kanchan Joshi --- include/linux/nvme.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/linux/nvme.h b/include/linux/nvme.h index d1cd53f2b6ab..4fad4aa245fb 100644 --- a/include/linux/nvme.h +++ b/include/linux/nvme.h @@ -642,6 +642,7 @@ enum { NVME_CMD_EFFECTS_CCC = 1 << 4, NVME_CMD_EFFECTS_CSE_MASK = GENMASK(18, 16), NVME_CMD_EFFECTS_UUID_SEL = 1 << 19, + NVME_CMD_EFFECTS_SCOPE_MASK = GENMASK(31, 20), }; struct nvme_effects_log { -- cgit v1.2.3 From 1f0ae22ab470946143485a02cc1cd7e05c0f9120 Mon Sep 17 00:00:00 2001 From: Moshe Shemesh Date: Mon, 12 Dec 2022 10:42:15 +0200 Subject: net/mlx5: E-Switch, properly handle ingress tagged packets on VST Fix SRIOV VST mode behavior to insert cvlan when a guest tag is already present in the frame. Previous VST mode behavior was to drop packets or override existing tag, depending on the device version. In this patch we fix this behavior by correctly building the HW steering rule with a push vlan action, or for older devices we ask the FW to stack the vlan when a vlan is already present. Fixes: 07bab9502641 ("net/mlx5: E-Switch, Refactor eswitch ingress acl codes") Fixes: dfcb1ed3c331 ("net/mlx5: E-Switch, Vport ingress/egress ACLs rules for VST mode") Signed-off-by: Moshe Shemesh Reviewed-by: Mark Bloch Signed-off-by: Saeed Mahameed --- include/linux/mlx5/device.h | 5 +++++ include/linux/mlx5/mlx5_ifc.h | 3 ++- 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h index 5fe5d198b57a..29d4b201c7b2 100644 --- a/include/linux/mlx5/device.h +++ b/include/linux/mlx5/device.h @@ -1090,6 +1090,11 @@ enum { MLX5_VPORT_ADMIN_STATE_AUTO = 0x2, }; +enum { + MLX5_VPORT_CVLAN_INSERT_WHEN_NO_CVLAN = 0x1, + MLX5_VPORT_CVLAN_INSERT_ALWAYS = 0x3, +}; + enum { MLX5_L3_PROT_TYPE_IPV4 = 0, MLX5_L3_PROT_TYPE_IPV6 = 1, diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index f3d1c62c98dd..a9ee7bc59c90 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -913,7 +913,8 @@ struct mlx5_ifc_e_switch_cap_bits { u8 vport_svlan_insert[0x1]; u8 vport_cvlan_insert_if_not_exist[0x1]; u8 vport_cvlan_insert_overwrite[0x1]; - u8 reserved_at_5[0x2]; + u8 reserved_at_5[0x1]; + u8 vport_cvlan_insert_always[0x1]; u8 esw_shared_ingress_acl[0x1]; u8 esw_uplink_ingress_acl[0x1]; u8 root_ft_on_other_esw[0x1]; -- cgit v1.2.3 From 936a192f974018b4f6040f6f77b1cc1e75bd8666 Mon Sep 17 00:00:00 2001 From: Kuniyuki Iwashima Date: Mon, 26 Dec 2022 22:27:52 +0900 Subject: tcp: Add TIME_WAIT sockets in bhash2. Jiri Slaby reported regression of bind() with a simple repro. [0] The repro creates a TIME_WAIT socket and tries to bind() a new socket with the same local address and port. Before commit 28044fc1d495 ("net: Add a bhash2 table hashed by port and address"), the bind() failed with -EADDRINUSE, but now it succeeds. The cited commit should have put TIME_WAIT sockets into bhash2; otherwise, inet_bhash2_conflict() misses TIME_WAIT sockets when validating bind() requests if the address is not a wildcard one. The straight option is to move sk_bind2_node from struct sock to struct sock_common to add twsk to bhash2 as implemented as RFC. [1] However, the binary layout change in the struct sock could affect performances moving hot fields on different cachelines. To avoid that, we add another TIME_WAIT list in inet_bind2_bucket and check it while validating bind(). [0]: https://lore.kernel.org/netdev/6b971a4e-c7d8-411e-1f92-fda29b5b2fb9@kernel.org/ [1]: https://lore.kernel.org/netdev/20221221151258.25748-2-kuniyu@amazon.com/ Fixes: 28044fc1d495 ("net: Add a bhash2 table hashed by port and address") Reported-by: Jiri Slaby Suggested-by: Paolo Abeni Signed-off-by: Kuniyuki Iwashima Acked-by: Joanne Koong Signed-off-by: David S. Miller --- include/net/inet_hashtables.h | 4 ++++ include/net/inet_timewait_sock.h | 5 +++++ 2 files changed, 9 insertions(+) (limited to 'include') diff --git a/include/net/inet_hashtables.h b/include/net/inet_hashtables.h index 69174093078f..99bd823e97f6 100644 --- a/include/net/inet_hashtables.h +++ b/include/net/inet_hashtables.h @@ -108,6 +108,10 @@ struct inet_bind2_bucket { struct hlist_node node; /* List of sockets hashed to this bucket */ struct hlist_head owners; + /* bhash has twsk in owners, but bhash2 has twsk in + * deathrow not to add a member in struct sock_common. + */ + struct hlist_head deathrow; }; static inline struct net *ib_net(const struct inet_bind_bucket *ib) diff --git a/include/net/inet_timewait_sock.h b/include/net/inet_timewait_sock.h index 5b47545f22d3..4a8e578405cb 100644 --- a/include/net/inet_timewait_sock.h +++ b/include/net/inet_timewait_sock.h @@ -73,9 +73,14 @@ struct inet_timewait_sock { u32 tw_priority; struct timer_list tw_timer; struct inet_bind_bucket *tw_tb; + struct inet_bind2_bucket *tw_tb2; + struct hlist_node tw_bind2_node; }; #define tw_tclass tw_tos +#define twsk_for_each_bound_bhash2(__tw, list) \ + hlist_for_each_entry(__tw, list, tw_bind2_node) + static inline struct inet_timewait_sock *inet_twsk(const struct sock *sk) { return (struct inet_timewait_sock *)sk; -- cgit v1.2.3 From 99cb0d917ffa1ab628bb67364ca9b162c07699b1 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 27 Dec 2022 03:45:37 +0900 Subject: arch: fix broken BuildID for arm64 and riscv Dennis Gilmore reports that the BuildID is missing in the arm64 vmlinux since commit 994b7ac1697b ("arm64: remove special treatment for the link order of head.o"). The issue is that the type of .notes section, which contains the BuildID, changed from NOTES to PROGBITS. Ard Biesheuvel figured out that whichever object gets linked first gets to decide the type of a section. The PROGBITS type is the result of the compiler emitting .note.GNU-stack as PROGBITS rather than NOTE. While Ard provided a fix for arm64, I want to fix this globally because the same issue is happening on riscv since commit 2348e6bf4421 ("riscv: remove special treatment for the link order of head.o"). This problem will happen in general for other architectures if they start to drop unneeded entries from scripts/head-object-list.txt. Discard .note.GNU-stack in include/asm-generic/vmlinux.lds.h. Link: https://lore.kernel.org/lkml/CAABkxwuQoz1CTbyb57n0ZX65eSYiTonFCU8-LCQc=74D=xE=rA@mail.gmail.com/ Fixes: 994b7ac1697b ("arm64: remove special treatment for the link order of head.o") Fixes: 2348e6bf4421 ("riscv: remove special treatment for the link order of head.o") Reported-by: Dennis Gilmore Suggested-by: Ard Biesheuvel Signed-off-by: Masahiro Yamada Acked-by: Palmer Dabbelt --- include/asm-generic/vmlinux.lds.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h index a94219e9916f..659bf3b31c91 100644 --- a/include/asm-generic/vmlinux.lds.h +++ b/include/asm-generic/vmlinux.lds.h @@ -891,7 +891,12 @@ #define PRINTK_INDEX #endif +/* + * Discard .note.GNU-stack, which is emitted as PROGBITS by the compiler. + * Otherwise, the type of .notes section would become PROGBITS instead of NOTES. + */ #define NOTES \ + /DISCARD/ : { *(.note.GNU-stack) } \ .notes : AT(ADDR(.notes) - LOAD_OFFSET) { \ BOUNDED_SECTION_BY(.note.*, _notes) \ } NOTES_HEADERS \ -- cgit v1.2.3 From d9dba91be71f03cc75bcf39fc0d5d99ff33f1ae0 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Thu, 29 Dec 2022 17:33:33 +0100 Subject: net: dsa: tag_qca: fix wrong MGMT_DATA2 size It was discovered that MGMT_DATA2 can contain up to 28 bytes of data instead of the 12 bytes written in the Documentation by accounting the limit of 16 bytes declared in Documentation subtracting the first 4 byte in the packet header. Update the define with the real world value. Tested-by: Ronald Wahl Fixes: c2ee8181fddb ("net: dsa: tag_qca: add define for handling mgmt Ethernet packet") Signed-off-by: Christian Marangi Cc: stable@vger.kernel.org # v5.18+ Signed-off-by: David S. Miller --- include/linux/dsa/tag_qca.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/linux/dsa/tag_qca.h b/include/linux/dsa/tag_qca.h index b1b5720d89a5..ee657452f122 100644 --- a/include/linux/dsa/tag_qca.h +++ b/include/linux/dsa/tag_qca.h @@ -45,8 +45,8 @@ struct sk_buff; QCA_HDR_MGMT_COMMAND_LEN + \ QCA_HDR_MGMT_DATA1_LEN) -#define QCA_HDR_MGMT_DATA2_LEN 12 /* Other 12 byte for the mdio data */ -#define QCA_HDR_MGMT_PADDING_LEN 34 /* Padding to reach the min Ethernet packet */ +#define QCA_HDR_MGMT_DATA2_LEN 28 /* Other 28 byte for the mdio data */ +#define QCA_HDR_MGMT_PADDING_LEN 18 /* Padding to reach the min Ethernet packet */ #define QCA_HDR_MGMT_PKT_LEN (QCA_HDR_MGMT_HEADER_LEN + \ QCA_HDR_LEN + \ -- cgit v1.2.3 From 6d4cfcf97986cc67635630a2bc1f8d5c92ecdbba Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Thu, 29 Dec 2022 15:21:20 -0500 Subject: net: phy: Update documentation for get_rate_matching Now that phylink no longer calls phy_get_rate_matching with PHY_INTERFACE_MODE_NA, phys no longer need to support it. Remove the documentation mandating support. Fixes: 7642cc28fd37 ("net: phylink: fix PHY validation with rate adaption") Signed-off-by: Sean Anderson Signed-off-by: David S. Miller --- include/linux/phy.h | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'include') diff --git a/include/linux/phy.h b/include/linux/phy.h index 71eeb4e3b1fd..6378c997ded5 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -826,10 +826,7 @@ struct phy_driver { * whether to advertise lower-speed modes for that interface. It is * assumed that if a rate matching mode is supported on an interface, * then that interface's rate can be adapted to all slower link speeds - * supported by the phy. If iface is %PHY_INTERFACE_MODE_NA, and the phy - * supports any kind of rate matching for any interface, then it must - * return that rate matching mode (preferring %RATE_MATCH_PAUSE to - * %RATE_MATCH_CRS). If the interface is not supported, this should + * supported by the phy. If the interface is not supported, this should * return %RATE_MATCH_NONE. */ int (*get_rate_matching)(struct phy_device *phydev, -- cgit v1.2.3 From 5e29dc36bd5e2166b834ceb19990d9e68a734d7d Mon Sep 17 00:00:00 2001 From: Jozsef Kadlecsik Date: Fri, 30 Dec 2022 13:24:38 +0100 Subject: netfilter: ipset: Rework long task execution when adding/deleting entries When adding/deleting large number of elements in one step in ipset, it can take a reasonable amount of time and can result in soft lockup errors. The patch 5f7b51bf09ba ("netfilter: ipset: Limit the maximal range of consecutive elements to add/delete") tried to fix it by limiting the max elements to process at all. However it was not enough, it is still possible that we get hung tasks. Lowering the limit is not reasonable, so the approach in this patch is as follows: rely on the method used at resizing sets and save the state when we reach a smaller internal batch limit, unlock/lock and proceed from the saved state. Thus we can avoid long continuous tasks and at the same time removed the limit to add/delete large number of elements in one step. The nfnl mutex is held during the whole operation which prevents one to issue other ipset commands in parallel. Fixes: 5f7b51bf09ba ("netfilter: ipset: Limit the maximal range of consecutive elements to add/delete") Reported-by: syzbot+9204e7399656300bf271@syzkaller.appspotmail.com Signed-off-by: Jozsef Kadlecsik Signed-off-by: Pablo Neira Ayuso --- include/linux/netfilter/ipset/ip_set.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/linux/netfilter/ipset/ip_set.h b/include/linux/netfilter/ipset/ip_set.h index ab934ad951a8..e8c350a3ade1 100644 --- a/include/linux/netfilter/ipset/ip_set.h +++ b/include/linux/netfilter/ipset/ip_set.h @@ -197,7 +197,7 @@ struct ip_set_region { }; /* Max range where every element is added/deleted in one step */ -#define IPSET_MAX_RANGE (1<<20) +#define IPSET_MAX_RANGE (1<<14) /* The max revision number supported by any set type + 1 */ #define IPSET_REVISION_MAX 9 -- cgit v1.2.3