From 4166a56aa8d5babe979d8e0834a741c9f015ad14 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 20 May 2017 23:42:50 +0200 Subject: ARM/dmaengine: pl08x: pass reasonable memcpy settings We cannot use bits from configuration registers as API between platforms and driver like this, abstract it out to two enums and mimic the stuff passed as device tree data. This is done to make it possible for the driver to generate the ccfg word on-the-fly so we can support more PL08x derivatives. Acked-by: Olof Johansson Acked-by: Arnd Bergmann Signed-off-by: Linus Walleij Signed-off-by: Vinod Koul --- include/linux/amba/pl08x.h | 30 ++++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) (limited to 'include/linux') diff --git a/include/linux/amba/pl08x.h b/include/linux/amba/pl08x.h index 5308eae9ce35..79d1bcee738d 100644 --- a/include/linux/amba/pl08x.h +++ b/include/linux/amba/pl08x.h @@ -47,8 +47,6 @@ enum { * devices with static assignments * @muxval: a number usually used to poke into some mux regiser to * mux in the signal to this channel - * @cctl_memcpy: options for the channel control register for memcpy - * *** not used for slave channels *** * @addr: source/target address in physical memory for this DMA channel, * can be the address of a FIFO register for burst requests for example. * This can be left undefined if the PrimeCell API is used for configuring @@ -63,12 +61,28 @@ struct pl08x_channel_data { int min_signal; int max_signal; u32 muxval; - u32 cctl_memcpy; dma_addr_t addr; bool single; u8 periph_buses; }; +enum pl08x_burst_size { + PL08X_BURST_SZ_1, + PL08X_BURST_SZ_4, + PL08X_BURST_SZ_8, + PL08X_BURST_SZ_16, + PL08X_BURST_SZ_32, + PL08X_BURST_SZ_64, + PL08X_BURST_SZ_128, + PL08X_BURST_SZ_256, +}; + +enum pl08x_bus_width { + PL08X_BUS_WIDTH_8_BITS, + PL08X_BUS_WIDTH_16_BITS, + PL08X_BUS_WIDTH_32_BITS, +}; + /** * struct pl08x_platform_data - the platform configuration for the PL08x * PrimeCells. @@ -76,6 +90,11 @@ struct pl08x_channel_data { * platform, all inclusive, including multiplexed channels. The available * physical channels will be multiplexed around these signals as they are * requested, just enumerate all possible channels. + * @num_slave_channels: number of elements in the slave channel array + * @memcpy_burst_size: the appropriate burst size for memcpy operations + * @memcpy_bus_width: memory bus width + * @memcpy_prot_buff: whether memcpy DMA is bufferable + * @memcpy_prot_cache: whether memcpy DMA is cacheable * @get_xfer_signal: request a physical signal to be used for a DMA transfer * immediately: if there is some multiplexing or similar blocking the use * of the channel the transfer can be denied by returning less than zero, @@ -90,7 +109,10 @@ struct pl08x_channel_data { struct pl08x_platform_data { struct pl08x_channel_data *slave_channels; unsigned int num_slave_channels; - struct pl08x_channel_data memcpy_channel; + enum pl08x_burst_size memcpy_burst_size; + enum pl08x_bus_width memcpy_bus_width; + bool memcpy_prot_buff; + bool memcpy_prot_cache; int (*get_xfer_signal)(const struct pl08x_channel_data *); void (*put_xfer_signal)(const struct pl08x_channel_data *, int); u8 lli_buses; -- cgit v1.2.3 From 1e1cfc7213a37131a53e7dfada75dce77b8e043d Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 20 May 2017 23:42:53 +0200 Subject: dmaengine: pl08x: Add support for Faraday Technology FTDMAC020 After reading the specs for the Faraday Technology FTDMAC020 found in the Gemini platform, it becomes pretty evident that this is just another PL08x derivative, and should be handled like such by simply extending the existing PL08x driver to handle the quirks in this hardware. This patch makes memcpy work and has been tested on the Gemini and also regression-tested on the Nomadik NHK15 using dmatest with 10 threads per channel without a hinch for hours. I have not implemented slave DMA in those codepaths, because this device (Gemini) does not use slave DMA, and it seems like devices using FTDMAC020 for device DMA have a slightly different register layout so some real hardware is needed to proceed with this. I left some FIXME etc in the code for this. I had to do some refactorings of some helper functions, but I have not split those into separate patches because these refactorings do not make much sense without the increased complexity of handling the FTDMAC020. The DMA test would hang the platform on me on the Gemini after a few thousand iterations, however after turning of the caches the problem immediately disappeared and I could run the DMA engine with 10 threads pers physical channel for days in a row without a crash. I think there is no problem with the DMA driver: instead it is something fishy in the FA526 cache handling code that get pretty heavily exercised by the DMA engine and we need to go and fix that instead. Signed-off-by: Linus Walleij Signed-off-by: Vinod Koul --- include/linux/amba/pl080.h | 83 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 82 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/amba/pl080.h b/include/linux/amba/pl080.h index 580b5323a717..10124c9f9db5 100644 --- a/include/linux/amba/pl080.h +++ b/include/linux/amba/pl080.h @@ -44,7 +44,14 @@ #define PL080_SYNC (0x34) -/* Per channel configuration registers */ +/* The Faraday Technology FTDMAC020 variant registers */ +#define FTDMAC020_CH_BUSY (0x20) +/* Identical to PL080_CONFIG */ +#define FTDMAC020_CSR (0x24) +/* Identical to PL080_SYNC */ +#define FTDMAC020_SYNC (0x2C) +#define FTDMAC020_REVISION (0x30) +#define FTDMAC020_FEATURE (0x34) /* Per channel configuration registers */ #define PL080_Cx_BASE(x) ((0x100 + (x * 0x20))) @@ -55,6 +62,13 @@ #define PL080_CH_CONFIG (0x10) #define PL080S_CH_CONTROL2 (0x10) #define PL080S_CH_CONFIG (0x14) +/* The Faraday FTDMAC020 derivative shuffles the registers around */ +#define FTDMAC020_CH_CSR (0x00) +#define FTDMAC020_CH_CFG (0x04) +#define FTDMAC020_CH_SRC_ADDR (0x08) +#define FTDMAC020_CH_DST_ADDR (0x0C) +#define FTDMAC020_CH_LLP (0x10) +#define FTDMAC020_CH_SIZE (0x14) #define PL080_LLI_ADDR_MASK (0x3fffffff << 2) #define PL080_LLI_ADDR_SHIFT (2) @@ -119,6 +133,73 @@ #define PL080_FLOW_PER2MEM_PER (0x6) #define PL080_FLOW_SRC2DST_SRC (0x7) +#define FTDMAC020_CH_CSR_TC_MSK BIT(31) +/* Later versions have a threshold in bits 24..26, */ +#define FTDMAC020_CH_CSR_FIFOTH_MSK (0x7 << 24) +#define FTDMAC020_CH_CSR_FIFOTH_SHIFT (24) +#define FTDMAC020_CH_CSR_CHPR1_MSK (0x3 << 22) +#define FTDMAC020_CH_CSR_PROT3 BIT(21) +#define FTDMAC020_CH_CSR_PROT2 BIT(20) +#define FTDMAC020_CH_CSR_PROT1 BIT(19) +#define FTDMAC020_CH_CSR_SRC_SIZE_MSK (0x7 << 16) +#define FTDMAC020_CH_CSR_SRC_SIZE_SHIFT (16) +#define FTDMAC020_CH_CSR_ABT BIT(15) +#define FTDMAC020_CH_CSR_SRC_WIDTH_MSK (0x7 << 11) +#define FTDMAC020_CH_CSR_SRC_WIDTH_SHIFT (11) +#define FTDMAC020_CH_CSR_DST_WIDTH_MSK (0x7 << 8) +#define FTDMAC020_CH_CSR_DST_WIDTH_SHIFT (8) +#define FTDMAC020_CH_CSR_MODE BIT(7) +/* 00 = increase, 01 = decrease, 10 = fix */ +#define FTDMAC020_CH_CSR_SRCAD_CTL_MSK (0x3 << 5) +#define FTDMAC020_CH_CSR_SRCAD_CTL_SHIFT (5) +#define FTDMAC020_CH_CSR_DSTAD_CTL_MSK (0x3 << 3) +#define FTDMAC020_CH_CSR_DSTAD_CTL_SHIFT (3) +#define FTDMAC020_CH_CSR_SRC_SEL BIT(2) +#define FTDMAC020_CH_CSR_DST_SEL BIT(1) +#define FTDMAC020_CH_CSR_EN BIT(0) + +/* FIFO threshold setting */ +#define FTDMAC020_CH_CSR_FIFOTH_1 (0x0) +#define FTDMAC020_CH_CSR_FIFOTH_2 (0x1) +#define FTDMAC020_CH_CSR_FIFOTH_4 (0x2) +#define FTDMAC020_CH_CSR_FIFOTH_8 (0x3) +#define FTDMAC020_CH_CSR_FIFOTH_16 (0x4) +/* The FTDMAC020 supports 64bit wide transfers */ +#define FTDMAC020_WIDTH_64BIT (0x3) +/* Address can be increased, decreased or fixed */ +#define FTDMAC020_CH_CSR_SRCAD_CTL_INC (0x0) +#define FTDMAC020_CH_CSR_SRCAD_CTL_DEC (0x1) +#define FTDMAC020_CH_CSR_SRCAD_CTL_FIXED (0x2) + +#define FTDMAC020_CH_CFG_LLP_CNT_MASK (0xf << 16) +#define FTDMAC020_CH_CFG_LLP_CNT_SHIFT (16) +#define FTDMAC020_CH_CFG_BUSY BIT(8) +#define FTDMAC020_CH_CFG_INT_ABT_MASK BIT(2) +#define FTDMAC020_CH_CFG_INT_ERR_MASK BIT(1) +#define FTDMAC020_CH_CFG_INT_TC_MASK BIT(0) + +/* Inside the LLIs, the applicable CSR fields are mapped differently */ +#define FTDMAC020_LLI_TC_MSK BIT(28) +#define FTDMAC020_LLI_SRC_WIDTH_MSK (0x7 << 25) +#define FTDMAC020_LLI_SRC_WIDTH_SHIFT (25) +#define FTDMAC020_LLI_DST_WIDTH_MSK (0x7 << 22) +#define FTDMAC020_LLI_DST_WIDTH_SHIFT (22) +#define FTDMAC020_LLI_SRCAD_CTL_MSK (0x3 << 20) +#define FTDMAC020_LLI_SRCAD_CTL_SHIFT (20) +#define FTDMAC020_LLI_DSTAD_CTL_MSK (0x3 << 18) +#define FTDMAC020_LLI_DSTAD_CTL_SHIFT (18) +#define FTDMAC020_LLI_SRC_SEL BIT(17) +#define FTDMAC020_LLI_DST_SEL BIT(16) +#define FTDMAC020_LLI_TRANSFER_SIZE_MASK (0xfff << 0) +#define FTDMAC020_LLI_TRANSFER_SIZE_SHIFT (0) + +#define FTDMAC020_CFG_LLP_CNT_MASK (0x0f << 16) +#define FTDMAC020_CFG_LLP_CNT_SHIFT (16) +#define FTDMAC020_CFG_BUSY BIT(8) +#define FTDMAC020_CFG_INT_ABT_MSK BIT(2) +#define FTDMAC020_CFG_INT_ERR_MSK BIT(1) +#define FTDMAC020_CFG_INT_TC_MSK BIT(0) + /* DMA linked list chain structure */ struct pl080_lli { -- cgit v1.2.3 From fcc785417fba2dc81d2f6ba888caaff463f4f441 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 20 May 2017 23:42:54 +0200 Subject: dmaengine: pl08x: use GENMASK() to create bitmasks This switches the arbitrary shifting of hex constants in the pl080 header to use GENMASK(). Suggested-by: Vinod Koul Signed-off-by: Linus Walleij Signed-off-by: Vinod Koul --- include/linux/amba/pl080.h | 50 +++++++++++++++++++++++----------------------- 1 file changed, 25 insertions(+), 25 deletions(-) (limited to 'include/linux') diff --git a/include/linux/amba/pl080.h b/include/linux/amba/pl080.h index 10124c9f9db5..ab036b6b1804 100644 --- a/include/linux/amba/pl080.h +++ b/include/linux/amba/pl080.h @@ -70,12 +70,12 @@ #define FTDMAC020_CH_LLP (0x10) #define FTDMAC020_CH_SIZE (0x14) -#define PL080_LLI_ADDR_MASK (0x3fffffff << 2) +#define PL080_LLI_ADDR_MASK GENMASK(31, 2) #define PL080_LLI_ADDR_SHIFT (2) #define PL080_LLI_LM_AHB2 BIT(0) #define PL080_CONTROL_TC_IRQ_EN BIT(31) -#define PL080_CONTROL_PROT_MASK (0x7 << 28) +#define PL080_CONTROL_PROT_MASK GENMASK(30, 28) #define PL080_CONTROL_PROT_SHIFT (28) #define PL080_CONTROL_PROT_CACHE BIT(30) #define PL080_CONTROL_PROT_BUFF BIT(29) @@ -84,16 +84,16 @@ #define PL080_CONTROL_SRC_INCR BIT(26) #define PL080_CONTROL_DST_AHB2 BIT(25) #define PL080_CONTROL_SRC_AHB2 BIT(24) -#define PL080_CONTROL_DWIDTH_MASK (0x7 << 21) +#define PL080_CONTROL_DWIDTH_MASK GENMASK(23, 21) #define PL080_CONTROL_DWIDTH_SHIFT (21) -#define PL080_CONTROL_SWIDTH_MASK (0x7 << 18) +#define PL080_CONTROL_SWIDTH_MASK GENMASK(20, 18) #define PL080_CONTROL_SWIDTH_SHIFT (18) -#define PL080_CONTROL_DB_SIZE_MASK (0x7 << 15) +#define PL080_CONTROL_DB_SIZE_MASK GENMASK(17, 15) #define PL080_CONTROL_DB_SIZE_SHIFT (15) -#define PL080_CONTROL_SB_SIZE_MASK (0x7 << 12) +#define PL080_CONTROL_SB_SIZE_MASK GENMASK(14, 12) #define PL080_CONTROL_SB_SIZE_SHIFT (12) -#define PL080_CONTROL_TRANSFER_SIZE_MASK (0xfff << 0) -#define PL080S_CONTROL_TRANSFER_SIZE_MASK (0x1ffffff << 0) +#define PL080_CONTROL_TRANSFER_SIZE_MASK GENMASK(11, 0) +#define PL080S_CONTROL_TRANSFER_SIZE_MASK GENMASK(24, 0) #define PL080_CONTROL_TRANSFER_SIZE_SHIFT (0) #define PL080_BSIZE_1 (0x0) @@ -116,11 +116,11 @@ #define PL080_CONFIG_LOCK BIT(16) #define PL080_CONFIG_TC_IRQ_MASK BIT(15) #define PL080_CONFIG_ERR_IRQ_MASK BIT(14) -#define PL080_CONFIG_FLOW_CONTROL_MASK (0x7 << 11) +#define PL080_CONFIG_FLOW_CONTROL_MASK GENMASK(13, 11) #define PL080_CONFIG_FLOW_CONTROL_SHIFT (11) -#define PL080_CONFIG_DST_SEL_MASK (0xf << 6) +#define PL080_CONFIG_DST_SEL_MASK GENMASK(9, 6) #define PL080_CONFIG_DST_SEL_SHIFT (6) -#define PL080_CONFIG_SRC_SEL_MASK (0xf << 1) +#define PL080_CONFIG_SRC_SEL_MASK GENMASK(4, 1) #define PL080_CONFIG_SRC_SEL_SHIFT (1) #define PL080_CONFIG_ENABLE BIT(0) @@ -135,24 +135,24 @@ #define FTDMAC020_CH_CSR_TC_MSK BIT(31) /* Later versions have a threshold in bits 24..26, */ -#define FTDMAC020_CH_CSR_FIFOTH_MSK (0x7 << 24) +#define FTDMAC020_CH_CSR_FIFOTH_MSK GENMASK(26, 24) #define FTDMAC020_CH_CSR_FIFOTH_SHIFT (24) -#define FTDMAC020_CH_CSR_CHPR1_MSK (0x3 << 22) +#define FTDMAC020_CH_CSR_CHPR1_MSK GENMASK(23, 22) #define FTDMAC020_CH_CSR_PROT3 BIT(21) #define FTDMAC020_CH_CSR_PROT2 BIT(20) #define FTDMAC020_CH_CSR_PROT1 BIT(19) -#define FTDMAC020_CH_CSR_SRC_SIZE_MSK (0x7 << 16) +#define FTDMAC020_CH_CSR_SRC_SIZE_MSK GENMASK(18, 16) #define FTDMAC020_CH_CSR_SRC_SIZE_SHIFT (16) #define FTDMAC020_CH_CSR_ABT BIT(15) -#define FTDMAC020_CH_CSR_SRC_WIDTH_MSK (0x7 << 11) +#define FTDMAC020_CH_CSR_SRC_WIDTH_MSK GENMASK(13, 11) #define FTDMAC020_CH_CSR_SRC_WIDTH_SHIFT (11) -#define FTDMAC020_CH_CSR_DST_WIDTH_MSK (0x7 << 8) +#define FTDMAC020_CH_CSR_DST_WIDTH_MSK GENMASK(10, 8) #define FTDMAC020_CH_CSR_DST_WIDTH_SHIFT (8) #define FTDMAC020_CH_CSR_MODE BIT(7) /* 00 = increase, 01 = decrease, 10 = fix */ -#define FTDMAC020_CH_CSR_SRCAD_CTL_MSK (0x3 << 5) +#define FTDMAC020_CH_CSR_SRCAD_CTL_MSK GENMASK(6, 5) #define FTDMAC020_CH_CSR_SRCAD_CTL_SHIFT (5) -#define FTDMAC020_CH_CSR_DSTAD_CTL_MSK (0x3 << 3) +#define FTDMAC020_CH_CSR_DSTAD_CTL_MSK GENMASK(4, 3) #define FTDMAC020_CH_CSR_DSTAD_CTL_SHIFT (3) #define FTDMAC020_CH_CSR_SRC_SEL BIT(2) #define FTDMAC020_CH_CSR_DST_SEL BIT(1) @@ -171,7 +171,7 @@ #define FTDMAC020_CH_CSR_SRCAD_CTL_DEC (0x1) #define FTDMAC020_CH_CSR_SRCAD_CTL_FIXED (0x2) -#define FTDMAC020_CH_CFG_LLP_CNT_MASK (0xf << 16) +#define FTDMAC020_CH_CFG_LLP_CNT_MASK GENMASK(19, 16) #define FTDMAC020_CH_CFG_LLP_CNT_SHIFT (16) #define FTDMAC020_CH_CFG_BUSY BIT(8) #define FTDMAC020_CH_CFG_INT_ABT_MASK BIT(2) @@ -180,20 +180,20 @@ /* Inside the LLIs, the applicable CSR fields are mapped differently */ #define FTDMAC020_LLI_TC_MSK BIT(28) -#define FTDMAC020_LLI_SRC_WIDTH_MSK (0x7 << 25) +#define FTDMAC020_LLI_SRC_WIDTH_MSK GENMASK(27, 25) #define FTDMAC020_LLI_SRC_WIDTH_SHIFT (25) -#define FTDMAC020_LLI_DST_WIDTH_MSK (0x7 << 22) +#define FTDMAC020_LLI_DST_WIDTH_MSK GENMASK(24, 22) #define FTDMAC020_LLI_DST_WIDTH_SHIFT (22) -#define FTDMAC020_LLI_SRCAD_CTL_MSK (0x3 << 20) +#define FTDMAC020_LLI_SRCAD_CTL_MSK GENMASK(21, 20) #define FTDMAC020_LLI_SRCAD_CTL_SHIFT (20) -#define FTDMAC020_LLI_DSTAD_CTL_MSK (0x3 << 18) +#define FTDMAC020_LLI_DSTAD_CTL_MSK GENMASK(19, 18) #define FTDMAC020_LLI_DSTAD_CTL_SHIFT (18) #define FTDMAC020_LLI_SRC_SEL BIT(17) #define FTDMAC020_LLI_DST_SEL BIT(16) -#define FTDMAC020_LLI_TRANSFER_SIZE_MASK (0xfff << 0) +#define FTDMAC020_LLI_TRANSFER_SIZE_MASK GENMASK(11, 0) #define FTDMAC020_LLI_TRANSFER_SIZE_SHIFT (0) -#define FTDMAC020_CFG_LLP_CNT_MASK (0x0f << 16) +#define FTDMAC020_CFG_LLP_CNT_MASK GENMASK(19, 16) #define FTDMAC020_CFG_LLP_CNT_SHIFT (16) #define FTDMAC020_CFG_BUSY BIT(8) #define FTDMAC020_CFG_INT_ABT_MSK BIT(2) -- cgit v1.2.3