From 61b5deb5a968f7a82124f9b2591a6a151ed7273a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 10 Apr 2026 13:10:48 +0200 Subject: dt-bindings: pinctrl: nvidia,tegra234: Add missing required block Binding should require 'reg' property, because address space cannot be missing in the hardware and is already needed by the Linux drivers. Require also 'compatible' by convention, although it is not strictly necessary. Fixes: 857982138b79 ("dt-bindings: pinctrl: Document Tegra234 pin controllers") Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml | 4 ++++ Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml | 4 ++++ 2 files changed, 8 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml index db8224dfba2c..56fb9cf763ef 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml @@ -58,6 +58,10 @@ patternProperties: drive_soc_gpio27_pee6, drive_ao_retention_n_pee2, drive_vcomp_alert_pee1, drive_hdmi_cec_pgg0 ] +required: + - compatible + - reg + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml index f5a3a881dec4..bd305a34eee2 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml @@ -115,6 +115,10 @@ patternProperties: drive_sdmmc1_dat2_pj4, drive_sdmmc1_dat1_pj3, drive_sdmmc1_dat0_pj2 ] +required: + - compatible + - reg + unevaluatedProperties: false examples: -- cgit v1.2.3 From 39dcfa63dc479c97ba90170b972116030a4e184d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 10 Apr 2026 13:10:49 +0200 Subject: dt-bindings: pinctrl: nvidia,tegra234: Correctly use additionalProperties The binding does not reference any other schema, thus should use "additionalProperties: false" to disallow any undocumented properties. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml | 2 +- Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml index 56fb9cf763ef..4910dc8e8aeb 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml @@ -62,7 +62,7 @@ required: - compatible - reg -unevaluatedProperties: false +additionalProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml index bd305a34eee2..52b3d40e8839 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml @@ -119,7 +119,7 @@ required: - compatible - reg -unevaluatedProperties: false +additionalProperties: false examples: - | -- cgit v1.2.3 From 58631a03cf647ea93c2060d87d45f0c019fbfbbc Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Wed, 15 Apr 2026 16:59:24 +0530 Subject: dt-bindings: pinctrl: qcom: add IPQ9650 pinctrl Add device tree bindings for IPQ9650 TLMM block. Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,ipq9650-tlmm.yaml | 118 +++++++++++++++++++++ 1 file changed, 118 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq9650-tlmm.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq9650-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9650-tlmm.yaml new file mode 100644 index 000000000000..549eaa6aa11b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9650-tlmm.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq9650-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ9650 TLMM pin controller + +maintainers: + - Bjorn Andersson + - Kathiravan Thirumoorthy + +description: + Top Level Mode Multiplexer pin controller in Qualcomm IPQ9650 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,ipq9650-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 27 + + gpio-line-names: + maxItems: 54 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-ipq9650-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-ipq9650-tlmm-state" + additionalProperties: false + +$defs: + qcom-ipq9650-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-4][0-9]|5[0-3])$" + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ atest_char_start, atest_char_status0, atest_char_status1, + atest_char_status2, atest_char_status3, atest_tic_en, + audio_pri_mclk_in0, audio_pri_mclk_out0, audio_pri_mclk_in1, + audio_pri_mclk_out1, audio_pri, audio_sec, audio_sec_mclk_in0, + audio_sec_mclk_out0, audio_sec_mclk_in1, audio_sec_mclk_out1, + core_voltage_0, core_voltage_1, core_voltage_2, core_voltage_3, + core_voltage_4, cri_rng0, cri_rng1, cri_rng2, dbg_out_clk, + gcc_plltest_bypassnl, gcc_plltest_resetn, gcc_tlmm, gpio, + mdc_mst, mdc_slv0, mdc_slv1, mdio_mst, mdio_slv, mdio_slv0, + mdio_slv1, pcie0_clk_req_n, pcie0_wake, pcie1_clk_req_n, + pcie1_wake, pcie2_clk_req_n, pcie2_wake, pcie3_clk_req_n, + pcie3_wake, pcie4_clk_req_n, pcie4_wake, pll_bist_sync, + pll_test, pwm, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, + qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, + qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, + qdss_traceclk_a, qdss_tracectl_a, qdss_tracedata_a, qspi_data, + qspi_clk, qspi_cs_n, qup_se0, qup_se1, qup_se2, qup_se3, + qup_se4, qup_se5, qup_se6, qup_se7, resout, rx_los0, rx_los1, + rx_los2, sdc_clk, sdc_cmd, sdc_data, tsens_max, tsn ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq9650-tlmm"; + reg = <0x01000000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 54>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + + qup-uart1-default-state { + pins = "gpio43", "gpio44"; + function = "qup_se6"; + drive-strength = <8>; + bias-pull-down; + }; + }; -- cgit v1.2.3 From 5502ca2ae63ce02f1c1ce03aea3135d606e91060 Mon Sep 17 00:00:00 2001 From: Alexander Koskovich Date: Thu, 23 Apr 2026 04:43:19 +0000 Subject: dt-bindings: pinctrl: qcom,eliza-tlmm: Split QUP lane mirror alternates Several QUP lanes have MIRA/MIRB mirror routings that let the same lane be muxed out on alternative GPIOs. On Eliza these were all collapsed under the base function name (e.g. qup1_se6), which prevented boards from selecting the mirror variants. Add explicit function names for each mirror lane, matching the pattern already established by qcom,sm8550-tlmm and related bindings. Signed-off-by: Alexander Koskovich Acked-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,eliza-tlmm.yaml | 25 +++++++++++++--------- 1 file changed, 15 insertions(+), 10 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml index 282650426487..be7b4680045f 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml @@ -86,16 +86,21 @@ $defs: qdss_gpio_tracectl, qdss_gpio_tracedata, qlink_big_enable, qlink_big_request, qlink_little_enable, qlink_little_request, qlink_wmss, qspi0, qspi_clk, - qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, - qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1, - qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6, - qup2_se7, resout_gpio, sd_write_protect, sdc1, sdc2, - sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, tmess_prng0, - tmess_prng1, tmess_prng2, tmess_prng3, tsense_pwm1, - tsense_pwm2, tsense_pwm3, tsense_pwm4, uim0_clk, - uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data, - uim1_present, uim1_reset, usb0_hs, usb_phy, vfr_0, vfr_1, - vsense_trigger_mirnat, wcn_sw_ctrl ] + qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se2_l2_mira, + qup1_se2_l2_mirb, qup1_se2_l3_mira, qup1_se2_l3_mirb, + qup1_se3, qup1_se4, qup1_se5, qup1_se6, qup1_se6_l1_mira, + qup1_se6_l1_mirb, qup1_se6_l3_mira, qup1_se6_l3_mirb, + qup1_se7, qup1_se7_l0_mira, qup1_se7_l0_mirb, + qup1_se7_l1_mira, qup1_se7_l1_mirb, qup2_se0, qup2_se1, + qup2_se2, qup2_se3, qup2_se3_l0_mira, qup2_se3_l0_mirb, + qup2_se3_l1_mira, qup2_se3_l1_mirb, qup2_se4, qup2_se5, + qup2_se6, qup2_se7, resout_gpio, sd_write_protect, sdc1, + sdc2, sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, + tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3, + tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4, + uim0_clk, uim0_data, uim0_present, uim0_reset, uim1_clk, + uim1_data, uim1_present, uim1_reset, usb0_hs, usb_phy, + vfr_0, vfr_1, vsense_trigger_mirnat, wcn_sw_ctrl ] required: - pins -- cgit v1.2.3 From 1bd5c56253c534840382d01f80e6a6a40ff01dd6 Mon Sep 17 00:00:00 2001 From: Alexander Koskovich Date: Thu, 23 Apr 2026 04:43:27 +0000 Subject: dt-bindings: pinctrl: qcom,eliza-tlmm: Split QUP1_SE4 lanes QUP1_SE4 shares GPIO_36 & GPIO_37 for both L0/L1 and L3/L2 so the function name cannot be the same or the alternate function cannot be selected. Split them up into individual lane functions so boards can specify. Signed-off-by: Alexander Koskovich Acked-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml index be7b4680045f..fa0177529277 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml @@ -88,7 +88,8 @@ $defs: qlink_little_request, qlink_wmss, qspi0, qspi_clk, qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se2_l2_mira, qup1_se2_l2_mirb, qup1_se2_l3_mira, qup1_se2_l3_mirb, - qup1_se3, qup1_se4, qup1_se5, qup1_se6, qup1_se6_l1_mira, + qup1_se3, qup1_se4_l0, qup1_se4_l1, qup1_se4_l2, + qup1_se4_l3, qup1_se5, qup1_se6, qup1_se6_l1_mira, qup1_se6_l1_mirb, qup1_se6_l3_mira, qup1_se6_l3_mirb, qup1_se7, qup1_se7_l0_mira, qup1_se7_l0_mirb, qup1_se7_l1_mira, qup1_se7_l1_mirb, qup2_se0, qup2_se1, -- cgit v1.2.3 From 1ea146943de776d0528facf031129420be64f07a Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Mon, 4 May 2026 12:07:25 +0200 Subject: dt-bindings: pinctrl: describe the Qualcomm nord-tlmm Add a DT binding document describing the TLMM pin controller available on the Nord platforms from Qualcomm. Co-developed-by: Shawn Guo Signed-off-by: Shawn Guo Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bartosz Golaszewski Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,nord-tlmm.yaml | 141 +++++++++++++++++++++ 1 file changed, 141 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml new file mode 100644 index 000000000000..4bb511719f31 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,nord-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SA8797P TLMM block + +maintainers: + - Bartosz Golaszewski + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SA8797P SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,nord-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 90 + + gpio-line-names: + maxItems: 181 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-nord-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-nord-tlmm-state" + additionalProperties: false + +$defs: + qcom-nord-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|180)$" + - enum: [ ufs_reset ] + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ aoss_cti, atest_char, atest_usb20, atest_usb21, + aud_intfc0_clk, aud_intfc0_data, aud_intfc0_ws, + aud_intfc10_clk, aud_intfc10_data, aud_intfc10_ws, + aud_intfc1_clk, aud_intfc1_data, aud_intfc1_ws, + aud_intfc2_clk, aud_intfc2_data, aud_intfc2_ws, + aud_intfc3_clk, aud_intfc3_data, aud_intfc3_ws, + aud_intfc4_clk, aud_intfc4_data, aud_intfc4_ws, + aud_intfc5_clk, aud_intfc5_data, aud_intfc5_ws, + aud_intfc6_clk, aud_intfc6_data, aud_intfc6_ws, + aud_intfc7_clk, aud_intfc7_data, aud_intfc7_ws, + aud_intfc8_clk, aud_intfc8_data, aud_intfc8_ws, + aud_intfc9_clk, aud_intfc9_data, aud_intfc9_ws, + aud_mclk0_mira, aud_mclk0_mirb, aud_mclk1_mira, aud_mclk1_mirb, + aud_mclk2_mira, aud_mclk2_mirb, aud_refclk0, aud_refclk1, + bist_done, ccu_async_in, ccu_i2c_scl, ccu_i2c_sda, ccu_timer, + clink_debug, dbg_out, dbg_out_clk, + ddr_bist_complete, ddr_bist_fail, ddr_bist_start, ddr_bist_stop, + ddr_pxi, dp_rx0, dp_rx00, dp_rx01, dp_rx0_mute, dp_rx1, dp_rx10, + dp_rx11, dp_rx1_mute, + edp0_hot, edp0_lcd, edp1_hot, edp1_lcd, edp2_hot, edp2_lcd, + edp3_hot, edp3_lcd, + emac0_mcg, emac0_mdc, emac0_mdio, emac0_ptp, emac1_mcg, + emac1_mdc, emac1_mdio, emac1_ptp, + gcc_gp1_clk, gcc_gp2_clk, gcc_gp3_clk, gcc_gp4_clk, gcc_gp5_clk, + gcc_gp6_clk, gcc_gp7_clk, gcc_gp8_clk, jitter_bist, lbist_pass, + mbist_pass, mdp0_vsync_out, mdp1_vsync_out, mdp_vsync_e, + mdp_vsync_p, mdp_vsync_s, + pcie0_clk_req_n, pcie1_clk_req_n, pcie2_clk_req_n, + pcie3_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux, + prng_rosc0, prng_rosc1, pwrbrk_i_n, qdss, qdss_cti, qspi, + qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, qup0_se5, + qup1_se0, qup1_se1, qup1_se3, qup1_se2, qup1_se4, qup1_se5, + qup1_se6, qup2_se0, qup2_se1, qup2_se2, qup2_se3, qup2_se4, + qup2_se5, qup2_se6, + sailss_ospi, sdc4_clk, sdc4_cmd, sdc4_data, smb_alert, + smb_alert_n, smb_clk, smb_dat, tb_trig_sdc4, tmess_prng0, + tmess_prng1, tsc_timer, tsense_pwm, usb0_hs, + usb0_phy_ps, usb1_hs, usb1_phy_ps, usb2_hs, usxgmii0_phy, + usxgmii1_phy, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@f100000 { + compatible = "qcom,nord-tlmm"; + reg = <0x0f100000 0xc0000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 181>; + wakeup-parent = <&pdc>; + + qup_uart15_default: qup-uart15-default-state { + pins = "gpio147", "gpio148"; + function = "qup2_se2"; + drive-strength = <2>; + bias-disable; + }; + }; +... -- cgit v1.2.3 From 9e5e1de61db29277d107bd6985c57629df449610 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 4 May 2026 19:54:36 -0400 Subject: dt-bindings: pinctrl: Add generic pinctrl for board-level mux chips MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a generic pinctrl binding for board-level pinmux chips that are controlled through the multiplexer subsystem. On some boards, especially development boards, external mux chips are used to switch SoC signals between different peripherals (e.g. MMC and UART). The mux select lines are often driven by a GPIO expander over I2C, as illustrated below: ┌──────┐ ┌─────┐ │ SOC │ │ │ ┌───────┐ │ │ │ │───►│ MMC │ │ │ │ MUX │ └───────┘ │ ├─────►│ │ ┌───────┐ │ │ │ │───►│ UART │ │ │ └─────┘ └───────┘ │ │ ▲ │ │ ┌────┴──────────────┐ │ I2C ├───►│ GPIO Expander │ └──────┘ └───────────────────┘ Traditionally, gpio-hog is used to configure the onboard mux at boot. However, the GPIO expander may probe later than consumer devices such as MMC. As a result, the MUX might not be configured when the peripheral driver probes, leading to initialization failures or data transfer errors. Introduce a generic pinctrl binding that models the board-level MUX as a pin control provider and builds proper device links between the MUX, its GPIO controller, and peripheral devices. This ensures correct probe ordering and reliable mux configuration. The implementation leverages the standard multiplexer subsystem, which provides broad support for onboard mux controllers and avoids the need for per-driver custom MUX handling. Allow pinctrl-* pattern as node name because this pinctrl device have not reg property. Reviewed-by: Linus Walleij Reviewed-by: Rob Herring (Arm) Signed-off-by: Frank Li Signed-off-by: Linus Walleij --- .../bindings/pinctrl/pinctrl-multiplexer.yaml | 57 ++++++++++++++++++++++ .../devicetree/bindings/pinctrl/pinctrl.yaml | 2 +- 2 files changed, 58 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-multiplexer.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-multiplexer.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-multiplexer.yaml new file mode 100644 index 000000000000..2b0385ed879b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-multiplexer.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/pinctrl-multiplexer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic pinctrl device for on-board MUX Chips + +maintainers: + - Frank Li + +description: + Generic pinctrl device for on-board MUX Chips, which switch SoC signals + between different peripherals (e.g. MMC and UART). + + The MUX select lines are often driven by a I2C GPIO expander. + +properties: + compatible: + const: pinctrl-multiplexer + +patternProperties: + '-grp$': + type: object + additionalProperties: false + properties: + mux-states: + maxItems: 1 + + required: + - mux-states + +required: + - compatible + +allOf: + - $ref: pinctrl.yaml# + +unevaluatedProperties: false + +examples: + - | + pinctrl-mux { + compatible = "pinctrl-multiplexer"; + + uart-grp { + mux-states = <&mux 0>; + }; + + spi-grp { + mux-states = <&mux 1>; + }; + + i2c-grp { + mux-states = <&mux 2>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl.yaml index 290438826c50..20176bf30747 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl.yaml @@ -27,7 +27,7 @@ description: | properties: $nodename: - pattern: "^(pinctrl|pinmux)(@[0-9a-f]+)?$" + pattern: "^(pinctrl|pinmux)(@[0-9a-f]+|-[a-z0-9]+)?$" "#pinctrl-cells": description: > -- cgit v1.2.3 From 8e9121cc761db8837352e9f5651402d04795bf59 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Thu, 30 Apr 2026 09:10:41 +0200 Subject: dt-bindings: pinctrl: qcom: Add SM6350 LPI pinctrl Add bindings for pin controller in Low Power Audio SubSystem (LPASS). Signed-off-by: Luca Weiss Reviewed-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- .../pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml | 124 +++++++++++++++++++++ 1 file changed, 124 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000000..4903b2d37d89 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6350 SoC LPASS LPI TLMM + +maintainers: + - Luca Weiss + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem + (LPASS) Low Power Island (LPI) of Qualcomm SM6350 SoC. + +properties: + compatible: + const: qcom,sm6350-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + - description: LPASS LPI MCC registers + + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: core + - const: audio + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm6350-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm6350-lpass-state" + additionalProperties: false + +$defs: + qcom-sm6350-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|1[0-4])$" + + function: + enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk, + dmic3_data, gpio, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk, + i2s2_data, i2s2_ws, qua_mi2s_data, qua_mi2s_sclk, qua_mi2s_ws, + swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_data, wsa_swr_clk, + wsa_swr_data ] + description: + Specify the alternative function to be configured for the specified + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + + lpass_tlmm: pinctrl@33c0000 { + compatible = "qcom,sm6350-lpass-lpi-pinctrl"; + reg = <0x033c0000 0x20000>, + <0x03550000 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 15>; + + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", + "audio"; + + i2s1_active: i2s1-active-state { + clk-pins { + pins = "gpio6"; + function = "i2s1_clk"; + drive-strength = <8>; + bias-disable; + output-high; + }; + + ws-pins { + pins = "gpio7"; + function = "i2s1_ws"; + drive-strength = <8>; + bias-disable; + output-high; + }; + + data-pins { + pins = "gpio8", "gpio9"; + function = "i2s1_data"; + drive-strength = <8>; + bias-disable; + output-high; + }; + }; + }; -- cgit v1.2.3 From 02622db8683bd3e5581ebb8991a6ed53a459e9f1 Mon Sep 17 00:00:00 2001 From: Swati Agarwal Date: Mon, 4 May 2026 12:19:36 +0530 Subject: dt-bindings: pinctrl: qcom: move gpio-hog schema to tlmm-common Qualcomm TLMM-based pin controllers share the same gpio-hog binding semantics across multiple SoCs. The gpio-hog pattern currently defined in qcom,ipq4019-pinctrl.yaml and qcom,sdm845-pinctrl.yaml are not SOC specific and applies to all TLMM controllers. Move the gpio-hog patternProperties definition to qcom,tlmm-common.yaml so that it can be reused by other Qualcomm TLMM pinctrl bindings and avoid schema duplication. Signed-off-by: Swati Agarwal Reviewed-by: Krzysztof Kozlowski Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.yaml | 5 ----- Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml | 5 ----- Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml | 6 ++++++ 3 files changed, 6 insertions(+), 10 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.yaml index cc5de9f77680..de9a3e67e1bb 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.yaml @@ -36,11 +36,6 @@ patternProperties: $ref: "#/$defs/qcom-ipq4019-tlmm-state" additionalProperties: false - "-hog(-[0-9]+)?$": - type: object - required: - - gpio-hog - $defs: qcom-ipq4019-tlmm-state: type: object diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml index 4fcac2e55b55..3b33daedc018 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml @@ -42,11 +42,6 @@ patternProperties: $ref: "#/$defs/qcom-sdm845-tlmm-state" additionalProperties: false - "-hog(-[0-9]+)?$": - type: object - required: - - gpio-hog - $defs: qcom-sdm845-tlmm-state: type: object diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml index aae3dcf6cac8..aec72e8c0621 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml @@ -51,6 +51,12 @@ properties: should not be accessed by the OS. Please see the ../gpio/gpio.txt for more information. +patternProperties: + "-hog(-[0-9]+)?$": + type: object + required: + - gpio-hog + allOf: - $ref: pinctrl.yaml# -- cgit v1.2.3 From 86dc1b92cdb343f8de51edf489bcdd8cb5517cf8 Mon Sep 17 00:00:00 2001 From: Billy Tsai Date: Wed, 6 May 2026 16:06:18 +0800 Subject: dt-bindings: pinctrl: Add aspeed,ast2700-soc0-pinctrl Add a device tree binding for the pin controller found in the ASPEED AST2700 SoC0. The controller manages various peripheral functions such as eMMC, USB, VGA DDC, JTAG, and PCIe root complex signals. Describe the AST2700 SoC0 pin controller using standard pin multiplexing and configuration properties. Signed-off-by: Billy Tsai Acked-by: Conor Dooley Signed-off-by: Linus Walleij --- .../pinctrl/aspeed,ast2700-soc0-pinctrl.yaml | 188 +++++++++++++++++++++ 1 file changed, 188 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml new file mode 100644 index 000000000000..407a64f28d49 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml @@ -0,0 +1,188 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED AST2700 SoC0 Pin Controller + +maintainers: + - Billy Tsai + +description: > + The AST2700 features a dual-SoC architecture with two interconnected SoCs, + each having its own System Control Unit (SCU) for independent pin control. + This pin controller manages the pin multiplexing for SoC0. + + The SoC0 pin controller manages pin functions including eMMC, VGA DDC, + dual USB3/USB2 ports (A and B), JTAG, and PCIe root complex interfaces. + +properties: + compatible: + const: aspeed,ast2700-soc0-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-state$': + description: | + Pin control state. + + If 'function' is present, the node describes a pinmux state and must + specify 'groups'. + + For pin configuration, exactly one of 'groups' or 'pins' must be + specified in each state node. Group-level configuration applies to all + pins in the group. Pin-level configuration may be supplied in a + separate state node for individual pins; when both group-level and + pin-level configuration apply to the same pin, the pin-level + configuration takes precedence. + + type: object + allOf: + - $ref: pinmux-node.yaml# + - $ref: pincfg-node.yaml# + - if: + required: + - function + then: + required: + - groups + - oneOf: + - required: + - groups + - required: + - pins + + additionalProperties: false + + properties: + function: + enum: + - EMMC + - JTAGDDR + - JTAGM0 + - JTAGPCIEA + - JTAGPCIEB + - JTAGPSP + - JTAGSSP + - JTAGTSP + - JTAGUSB3A + - JTAGUSB3B + - PCIERC0PERST + - PCIERC1PERST + - TSPRSTN + - UFSCLKI + - USB2AD0 + - USB2AD1 + - USB2AH + - USB2AHP + - USB2AHPD0 + - USB2AXH + - USB2AXH2B + - USB2AXHD1 + - USB2AXHP + - USB2AXHP2B + - USB2AXHPD1 + - USB2BD0 + - USB2BD1 + - USB2BH + - USB2BHP + - USB2BHPD0 + - USB2BXH + - USB2BXH2A + - USB2BXHD1 + - USB2BXHP + - USB2BXHP2A + - USB2BXHPD1 + - USB3AXH + - USB3AXH2B + - USB3AXHD + - USB3AXHP + - USB3AXHP2B + - USB3AXHPD + - USB3BXH + - USB3BXH2A + - USB3BXHD + - USB3BXHP + - USB3BXHP2A + - USB3BXHPD + - VB + - VGADDC + + groups: + enum: + - EMMCCDN + - EMMCG1 + - EMMCG4 + - EMMCG8 + - EMMCWPN + - JTAG0 + - PCIERC0PERST + - PCIERC1PERST + - TSPRSTN + - UFSCLKI + - USB2A + - USB2AAP + - USB2ABP + - USB2ADAP + - USB2AH + - USB2AHAP + - USB2B + - USB2BAP + - USB2BBP + - USB2BDBP + - USB2BH + - USB2BHBP + - USB3A + - USB3AAP + - USB3ABP + - USB3B + - USB3BAP + - USB3BBP + - VB0 + - VB1 + - VGADDC + + pins: + enum: + - AB13 + - AB14 + - AC13 + - AC14 + - AD13 + - AD14 + - AE13 + - AE14 + - AE15 + - AF13 + - AF14 + - AF15 + + drive-strength: + enum: [3, 6, 8, 11, 16, 18, 20, 23, 30, 32, 33, 35, 37, 38, 39, 41] + + bias-disable: true + bias-pull-up: true + bias-pull-down: true + +required: + - compatible + - reg + +allOf: + - $ref: pinctrl.yaml# + +additionalProperties: false + +examples: + - | + pinctrl@400 { + compatible = "aspeed,ast2700-soc0-pinctrl"; + reg = <0x400 0x318>; + emmc-state { + function = "EMMC"; + groups = "EMMCG1"; + }; + }; -- cgit v1.2.3 From 37193e5b112d0685d9caa562cd01837a7ba3d11d Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Mon, 4 May 2026 15:27:47 +0800 Subject: dt-bindings: pinctrl: mediatek: mt8188: allow gpio hogs Add gpio hogs subnode rules to the MT8188 pinctrl binding. Signed-off-by: Icenowy Zheng Acked-by: Conor Dooley Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml index e994b0c70dbf..1cf06e46f7bb 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml @@ -67,6 +67,11 @@ properties: # PIN CONFIGURATION NODES patternProperties: + "-hog(-[0-9]+)?$": + type: object + required: + - gpio-hog + '-pins$': type: object additionalProperties: false -- cgit v1.2.3 From 0942cdb8f4b14cbfdc1996c2c332c6402a203bf3 Mon Sep 17 00:00:00 2001 From: Luca Leonardo Scorcia Date: Mon, 20 Apr 2026 22:30:03 +0100 Subject: dt-bindings: pinctrl: mediatek,mt65xx: Add MT6392 pinctrl Add a compatible for the pinctrl device of the MT6392 PMIC, a variant of the already supported MT6397. Signed-off-by: Luca Leonardo Scorcia Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml index aa71398cf522..1468c6f87cfa 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -17,6 +17,7 @@ properties: enum: - mediatek,mt2701-pinctrl - mediatek,mt2712-pinctrl + - mediatek,mt6392-pinctrl - mediatek,mt6397-pinctrl - mediatek,mt7623-pinctrl - mediatek,mt8127-pinctrl -- cgit v1.2.3 From c1bf20b2f449e914b0a6a607a6ee717f902850a7 Mon Sep 17 00:00:00 2001 From: Komal Bajaj Date: Tue, 12 May 2026 18:55:43 +0530 Subject: dt-bindings: pinctrl: qcom: Document Shikra Top Level Mode Multiplexer Add a DeviceTree binding to describe the TLMM block on Qualcomm's Shikra SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Komal Bajaj Reviewed-by: Bjorn Andersson Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,shikra-tlmm.yaml | 123 +++++++++++++++++++++ 1 file changed, 123 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,shikra-tlmm.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,shikra-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,shikra-tlmm.yaml new file mode 100644 index 000000000000..411c402f9044 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,shikra-tlmm.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,shikra-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Shikra TLMM block + +maintainers: + - Komal Bajaj + +description: | + Top Level Mode Multiplexer pin controller in Qualcomm Shikra SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,shikra-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 83 + + gpio-line-names: + maxItems: 166 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-shikra-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-shikra-tlmm-state" + additionalProperties: false + +$defs: + qcom-shikra-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-5][0-9]|16[0-5])$" + - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, + sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ gpio, agera_pll, atest_bbrx, atest_char, atest_gpsadc, + atest_tsens, atest_usb, cam_mclk, cci_async, cci_i2c0, + cci_i2c1, cci_timer, char_exec, cri_trng, dac_calib, + dbg_out_clk, ddr_bist, ddr_pxi, dmic, emac_dll, emac_mcg, + emac_phy, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux, + emac1_ptp_pps, ext_mclk, gcc_gp, gsm0_tx, i2s0, i2s1, + i2s2, i2s3, jitter_bist, m_voc, mdp_vsync_e, mdp_vsync_out0, + mdp_vsync_out1, mdp_vsync_p, mdp_vsync_s, mpm_pwr, mss_lte, + nav_gpio, pa_indicator_or, pbs_in, pbs_out, pcie0_clk_req_n, + phase_flag, pll, prng_rosc, pwm, qdss_cti, qup0_se0, + qup0_se1, qup0_se1_01, qup0_se1_23, qup0_se2, qup0_se3_01, + qup0_se3_23, qup0_se4_01, qup0_se4_23, qup0_se5, qup0_se6, + qup0_se7_01, qup0_se7_23, qup0_se8, qup0_se9, qup0_se9_01, + qup0_se9_23, rgmii, sd_write_protect, sdc_cdc, sdc_tb_trig, + ssbi_wtr, swr0_rx, swr0_tx, tgu_ch_trigout, tsc_async, + tsense_pwm, uim1, uim2, unused_adsp, unused_gsm1, usb0_phy_ps, + vfr, vsense_trigger_mirnat, wlan ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@500000 { + compatible = "qcom,shikra-tlmm"; + reg = <0x00500000 0x800000>; + + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio-ranges = <&tlmm 0 0 166>; + + qup-uart0-default-state { + pins = "gpio0", "gpio1"; + function = "qup0_se1"; + drive-strength = <2>; + bias-disable; + }; + }; +... -- cgit v1.2.3 From 30a0d3eda1baebeaed58690f16a31b4ddca36314 Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Thu, 7 May 2026 22:34:07 -0700 Subject: dt-bindings: pinctrl: qcom,pmic-gpio: Document PM8010 GPIO support Update the binding documentation to include the compatible string for PM8010 PMIC which has 2 GPIO modules. Signed-off-by: Fenglin Wu Acked-by: Rob Herring (Arm) Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml | 3 +++ 1 file changed, 3 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml index 386c31e9c52b..b8109e6c2a10 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -30,6 +30,7 @@ properties: - qcom,pm7550-gpio - qcom,pm7550ba-gpio - qcom,pm8005-gpio + - qcom,pm8010-gpio - qcom,pm8018-gpio - qcom,pm8019-gpio - qcom,pm8038-gpio @@ -134,6 +135,7 @@ allOf: compatible: contains: enum: + - qcom,pm8010-gpio - qcom,pmi8950-gpio - qcom,pmr735d-gpio then: @@ -465,6 +467,7 @@ $defs: - gpio1-gpio10 for pm7325 - gpio1-gpio8 for pm7550ba - gpio1-gpio4 for pm8005 + - gpio1-gpio2 for pm8010 - gpio1-gpio6 for pm8018 - gpio1-gpio12 for pm8038 - gpio1-gpio40 for pm8058 -- cgit v1.2.3 From f2c49ae0ce2ea518c140cbd8fca352c5a6f43bd0 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Fri, 15 May 2026 14:21:51 +0300 Subject: dt-bindings: pinctrl: qcom,eliza-tlmm: Merge QUP1_SE4 lane functions QUP1_SE4 uses GPIO36 and GPIO37 for two selectable lane pairs. The previous split added one function name per lane. Since these are usually configured in pairs in devicetree, it makes more sense to have them grouped. So replace the per-lane qup1_se4_l[0-3] names with names for the two selectable pairs, qup1_se4_01 and qup1_se4_23. Fixes: 1bd5c56253c5 ("dt-bindings: pinctrl: qcom,eliza-tlmm: Split QUP1_SE4 lanes") Suggested-by: Bjorn Andersson Acked-by: Krzysztof Kozlowski Signed-off-by: Abel Vesa Reviewed-by: Bjorn Andersson Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml index fa0177529277..aaaeca8e7bb7 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml @@ -88,8 +88,8 @@ $defs: qlink_little_request, qlink_wmss, qspi0, qspi_clk, qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se2_l2_mira, qup1_se2_l2_mirb, qup1_se2_l3_mira, qup1_se2_l3_mirb, - qup1_se3, qup1_se4_l0, qup1_se4_l1, qup1_se4_l2, - qup1_se4_l3, qup1_se5, qup1_se6, qup1_se6_l1_mira, + qup1_se3, qup1_se4_01, qup1_se4_23, + qup1_se5, qup1_se6, qup1_se6_l1_mira, qup1_se6_l1_mirb, qup1_se6_l3_mira, qup1_se6_l3_mirb, qup1_se7, qup1_se7_l0_mira, qup1_se7_l0_mirb, qup1_se7_l1_mira, qup1_se7_l1_mirb, qup2_se0, qup2_se1, -- cgit v1.2.3 From ae20d41bc230efa5972aaf5b27cadf1ff022aee8 Mon Sep 17 00:00:00 2001 From: Billy Tsai Date: Thu, 21 May 2026 17:17:45 +0800 Subject: dt-bindings: pinctrl: Add aspeed,ast2700-soc1-pinctrl SoC1 in the AST2700 integrates its own pin controller responsible for pin multiplexing and pin configuration. The controller manages various peripheral functions such as eSPI, LPC, VPI, SD, UART, I2C, I3C, PWM and others through SCU registers. The binding reuses the standard pinmux and generic pin configuration schemas and does not introduce custom Devicetree properties. Acked-by: Conor Dooley Signed-off-by: Billy Tsai Signed-off-by: Linus Walleij --- .../pinctrl/aspeed,ast2700-soc1-pinctrl.yaml | 760 +++++++++++++++++++++ 1 file changed, 760 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml new file mode 100644 index 000000000000..76944fd14e2c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml @@ -0,0 +1,760 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED AST2700 SoC1 Pin Controller + +maintainers: + - Billy Tsai + +description: + The AST2700 features a dual-SoC architecture with two interconnected SoCs, + each having its own System Control Unit (SCU) for independent pin control. + This pin controller manages the pin multiplexing for SoC1. + + The SoC1 pin controller manages pin functions including eSPI, LPC and I2C, + among others. + +properties: + compatible: + const: aspeed,ast2700-soc1-pinctrl + reg: + maxItems: 1 + +patternProperties: + '-state$': + description: | + Pin control state. + + If `function` is present, the node describes a pinmux state and must + specify `groups`. + + For pin configuration, exactly one of `groups` or `pins` must be + specified in each state node. Group-level configuration applies to all + pins in the group. Pin-level configuration may be supplied in a + separate state node for individual pins; when both group-level and + pin-level configuration apply to the same pin, the pin-level + configuration takes precedence. + + type: object + allOf: + - $ref: pinmux-node.yaml# + - $ref: pincfg-node.yaml# + - if: + required: + - function + then: + required: + - groups + - oneOf: + - required: + - groups + - required: + - pins + additionalProperties: false + + properties: + function: + enum: + - ADC0 + - ADC1 + - ADC10 + - ADC11 + - ADC12 + - ADC13 + - ADC14 + - ADC15 + - ADC2 + - ADC3 + - ADC4 + - ADC5 + - ADC6 + - ADC7 + - ADC8 + - ADC9 + - AUXPWRGOOD0 + - AUXPWRGOOD1 + - CANBUS + - ESPI0 + - ESPI1 + - FSI0 + - FSI1 + - FSI2 + - FSI3 + - FWQSPI + - FWSPIABR + - FWWPN + - HBLED + - I2C0 + - I2C1 + - I2C10 + - I2C11 + - I2C12 + - I2C13 + - I2C14 + - I2C15 + - I2C2 + - I2C3 + - I2C4 + - I2C5 + - I2C6 + - I2C7 + - I2C8 + - I2C9 + - I2CF0 + - I2CF1 + - I2CF2 + - I3C0 + - I3C1 + - I3C10 + - I3C11 + - I3C12 + - I3C13 + - I3C14 + - I3C15 + - I3C2 + - I3C3 + - I3C4 + - I3C5 + - I3C6 + - I3C7 + - I3C8 + - I3C9 + - JTAGM1 + - LPC0 + - LPC1 + - LTPI + - MACLINK0 + - MACLINK1 + - MACLINK2 + - MDIO0 + - MDIO1 + - MDIO2 + - NCTS0 + - NCTS1 + - NCTS5 + - NCTS6 + - NDCD0 + - NDCD1 + - NDCD5 + - NDCD6 + - NDSR0 + - NDSR1 + - NDSR5 + - NDSR6 + - NDTR0 + - NDTR1 + - NDTR5 + - NDTR6 + - NRI0 + - NRI1 + - NRI5 + - NRI6 + - NRTS0 + - NRTS1 + - NRTS5 + - NRTS6 + - OSCCLK + - PCIERC + - PWM0 + - PWM1 + - PWM10 + - PWM11 + - PWM12 + - PWM13 + - PWM14 + - PWM15 + - PWM2 + - PWM3 + - PWM4 + - PWM5 + - PWM6 + - PWM7 + - PWM8 + - PWM9 + - QSPI0 + - QSPI1 + - QSPI2 + - RGMII0 + - RGMII1 + - RMII0 + - RMII0RCLKO + - RMII1 + - RMII1RCLKO + - SALT0 + - SALT1 + - SALT10 + - SALT11 + - SALT12 + - SALT13 + - SALT14 + - SALT15 + - SALT2 + - SALT3 + - SALT4 + - SALT5 + - SALT6 + - SALT7 + - SALT8 + - SALT9 + - SD + - SGMII + - SGPM0 + - SGPM1 + - SGPS + - SIOONCTRLN0 + - SIOONCTRLN1 + - SIOPBIN0 + - SIOPBIN1 + - SIOPBON0 + - SIOPBON1 + - SIOPWREQN0 + - SIOPWREQN1 + - SIOPWRGD1 + - SIOS3N0 + - SIOS3N1 + - SIOS5N0 + - SIOS5N1 + - SIOSCIN0 + - SIOSCIN1 + - SMON0 + - SMON1 + - SPI0 + - SPI0ABR + - SPI0CS1 + - SPI0WPN + - SPI1 + - SPI1ABR + - SPI1CS1 + - SPI1WPN + - SPI2 + - SPI2CS1 + - TACH0 + - TACH1 + - TACH10 + - TACH11 + - TACH12 + - TACH13 + - TACH14 + - TACH15 + - TACH2 + - TACH3 + - TACH4 + - TACH5 + - TACH6 + - TACH7 + - TACH8 + - TACH9 + - THRU0 + - THRU1 + - THRU2 + - THRU3 + - UART0 + - UART1 + - UART10 + - UART11 + - UART2 + - UART3 + - UART5 + - UART6 + - UART7 + - UART8 + - UART9 + - USB2C + - USB2D + - USBUART + - VGA + - VPI + - WDTRST0N + - WDTRST1N + - WDTRST2N + - WDTRST3N + - WDTRST4N + - WDTRST5N + - WDTRST6N + - WDTRST7N + + groups: + enum: + - ADC0 + - ADC1 + - ADC10 + - ADC11 + - ADC12 + - ADC13 + - ADC14 + - ADC15 + - ADC2 + - ADC3 + - ADC4 + - ADC5 + - ADC6 + - ADC7 + - ADC8 + - ADC9 + - AUXPWRGOOD0 + - AUXPWRGOOD1 + - CANBUS + - DI2C0 + - DI2C1 + - DI2C10 + - DI2C11 + - DI2C12 + - DI2C13 + - DI2C14 + - DI2C15 + - DI2C2 + - DI2C3 + - DI2C8 + - DI2C9 + - DSGPM0 + - ESPI0 + - ESPI1 + - FSI0 + - FSI1 + - FSI2 + - FSI3 + - FWQSPI + - FWSPIABR + - FWWPN + - HBLED + - HVI3C0 + - HVI3C1 + - HVI3C12 + - HVI3C13 + - HVI3C14 + - HVI3C15 + - HVI3C2 + - HVI3C3 + - I2C0 + - I2C1 + - I2C10 + - I2C11 + - I2C12 + - I2C13 + - I2C14 + - I2C15 + - I2C2 + - I2C3 + - I2C4 + - I2C5 + - I2C6 + - I2C7 + - I2C8 + - I2C9 + - I2CF0 + - I2CF1 + - I2CF2 + - I3C10 + - I3C11 + - I3C4 + - I3C5 + - I3C6 + - I3C7 + - I3C8 + - I3C9 + - JTAGM1 + - LPC0 + - LPC1 + - LTPI + - LTPI_PS_I2C0 + - LTPI_PS_I2C1 + - LTPI_PS_I2C2 + - LTPI_PS_I2C3 + - MACLINK0 + - MACLINK1 + - MACLINK2 + - MDIO0 + - MDIO1 + - MDIO2 + - NCTS0 + - NCTS1 + - NCTS5 + - NCTS6 + - NDCD0 + - NDCD1 + - NDCD5 + - NDCD6 + - NDSR0 + - NDSR1 + - NDSR5 + - NDSR6 + - NDTR0 + - NDTR1 + - NDTR5 + - NDTR6 + - NRI0 + - NRI1 + - NRI5 + - NRI6 + - NRTS0 + - NRTS1 + - NRTS5 + - NRTS6 + - OSCCLK + - PE2SGRSTN + - PWM0 + - PWM1 + - PWM10 + - PWM11 + - PWM12 + - PWM13 + - PWM14 + - PWM15 + - PWM2 + - PWM3 + - PWM4 + - PWM5 + - PWM6 + - PWM7 + - PWM8 + - PWM9 + - QSPI0 + - QSPI1 + - QSPI2 + - RGMII0 + - RGMII1 + - RMII0 + - RMII0RCLKO + - RMII1 + - RMII1RCLKO + - SALT0 + - SALT1 + - SALT10 + - SALT11 + - SALT12 + - SALT13 + - SALT14 + - SALT15 + - SALT2 + - SALT3 + - SALT4 + - SALT5 + - SALT6 + - SALT7 + - SALT8 + - SALT9 + - SD + - SGMII + - SGPM0 + - SGPM1 + - SGPS + - SIOONCTRLN0 + - SIOONCTRLN1 + - SIOPBIN0 + - SIOPBIN1 + - SIOPBON0 + - SIOPBON1 + - SIOPWREQN0 + - SIOPWREQN1 + - SIOPWRGD1 + - SIOS3N0 + - SIOS3N1 + - SIOS5N0 + - SIOS5N1 + - SIOSCIN0 + - SIOSCIN1 + - SMON0 + - SMON1 + - SPI0 + - SPI0ABR + - SPI0CS1 + - SPI0WPN + - SPI1 + - SPI1ABR + - SPI1CS1 + - SPI1WPN + - SPI2 + - SPI2CS1 + - TACH0 + - TACH1 + - TACH10 + - TACH11 + - TACH12 + - TACH13 + - TACH14 + - TACH15 + - TACH2 + - TACH3 + - TACH4 + - TACH5 + - TACH6 + - TACH7 + - TACH8 + - TACH9 + - THRU0 + - THRU1 + - THRU2 + - THRU3 + - UART0 + - UART1 + - UART10 + - UART11 + - UART2 + - UART3 + - UART5 + - UART6 + - UART7 + - UART8 + - UART9 + - USB2CD + - USB2CH + - USB2CU + - USB2CUD + - USB2DD + - USB2DH + - USBUART + - VGA + - VPI + - WDTRST0N + - WDTRST1N + - WDTRST2N + - WDTRST3N + - WDTRST4N + - WDTRST5N + - WDTRST6N + - WDTRST7N + + pins: + enum: + - A14 + - A15 + - A18 + - A19 + - A21 + - A22 + - A23 + - A24 + - A25 + - A26 + - A6 + - A7 + - A8 + - AA12 + - AA13 + - AA14 + - AA15 + - AA16 + - AA17 + - AA18 + - AA20 + - AA21 + - AA22 + - AA23 + - AA24 + - AA25 + - AA26 + - AB15 + - AB16 + - AB17 + - AB18 + - AB19 + - AB20 + - AB21 + - AB22 + - AB23 + - AB24 + - AB25 + - AB26 + - AC15 + - AC16 + - AC17 + - AC18 + - AC19 + - AC20 + - AC22 + - AC24 + - AC25 + - AC26 + - AD15 + - AD16 + - AD17 + - AD18 + - AD19 + - AD20 + - AD22 + - AD25 + - AD26 + - AE16 + - AE17 + - AE18 + - AE19 + - AE20 + - AE21 + - AE23 + - AE25 + - AE26 + - AF16 + - AF17 + - AF18 + - AF19 + - AF20 + - AF21 + - AF23 + - AF25 + - AF26 + - B10 + - B11 + - B12 + - B13 + - B14 + - B15 + - B16 + - B18 + - B19 + - B21 + - B22 + - B23 + - B24 + - B25 + - B26 + - B6 + - B7 + - B8 + - B9 + - C10 + - C11 + - C12 + - C13 + - C14 + - C15 + - C16 + - C17 + - C18 + - C19 + - C20 + - C23 + - C26 + - C6 + - C7 + - C8 + - C9 + - D10 + - D12 + - D14 + - D15 + - D19 + - D20 + - D24 + - D26 + - D7 + - D8 + - D9 + - E10 + - E11 + - E12 + - E13 + - E14 + - E26 + - E7 + - E8 + - E9 + - F10 + - F11 + - F12 + - F13 + - F14 + - F26 + - F7 + - F8 + - F9 + - G10 + - G11 + - G7 + - G8 + - G9 + - H10 + - H11 + - H7 + - H8 + - H9 + - J10 + - J11 + - J12 + - J13 + - J9 + - K12 + - K13 + - L12 + - M13 + - M14 + - M15 + - M16 + - N13 + - N14 + - N15 + - N25 + - N26 + - P13 + - P14 + - P25 + - P26 + - R14 + - R25 + - R26 + - T23 + - T24 + - U21 + - U22 + - U25 + - U26 + - V14 + - V16 + - V17 + - V18 + - V19 + - V20 + - V21 + - V22 + - V23 + - V24 + - W14 + - W16 + - W17 + - W18 + - W20 + - W21 + - W22 + - W25 + - W26 + - Y11 + - Y15 + - Y16 + - Y17 + - Y18 + - Y20 + - Y21 + - Y22 + - Y23 + - Y24 + - Y25 + - Y26 + + drive-strength: + enum: [4, 8, 12, 16] + + bias-disable: true + bias-pull-up: true + bias-pull-down: true + +required: + - compatible + - reg + +allOf: + - $ref: pinctrl.yaml# + +additionalProperties: false + +examples: + - | + pinctrl@400 { + compatible = "aspeed,ast2700-soc1-pinctrl"; + reg = <0x400 0x2A0>; + sgpm0-state { + function = "SGPM0"; + groups = "SGPM0"; + }; + }; -- cgit v1.2.3 From 9323f8a0e12ccd30f5855067924c41224e7364ca Mon Sep 17 00:00:00 2001 From: Prathamesh Shete Date: Mon, 27 Apr 2026 13:42:27 +0000 Subject: dt-bindings: pinctrl: Document Tegra238 pin controllers Tegra238 contains two pin controllers. Document their compatible strings and describe the list of pins and functions that they provide. Signed-off-by: Prathamesh Shete Reviewed-by: Krzysztof Kozlowski Reviewed-by: Jon Hunter Signed-off-by: Linus Walleij --- .../pinctrl/nvidia,tegra238-pinmux-aon.yaml | 82 ++++++++ .../pinctrl/nvidia,tegra238-pinmux-common.yaml | 73 +++++++ .../bindings/pinctrl/nvidia,tegra238-pinmux.yaml | 219 +++++++++++++++++++++ 3 files changed, 374 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-common.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml new file mode 100644 index 000000000000..ab9264d87c88 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra238-pinmux-aon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra238 AON Pinmux Controller + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + const: nvidia,tegra238-pinmux-aon + + reg: + maxItems: 1 + +patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra238-pinmux-common.yaml + + properties: + nvidia,pins: + items: + enum: [ bootv_ctl_n_paa0, soc_gpio00_paa1, vcomp_alert_paa2, + pwm1_paa3, batt_oc_paa4, soc_gpio04_paa5, + soc_gpio25_paa6, soc_gpio26_paa7, + hdmi_cec_pbb0, + spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2, + spi2_cs0_pcc3, spi2_cs1_pcc4, uart3_tx_pcc5, + uart3_rx_pcc6, gen2_i2c_scl_pcc7, + gen2_i2c_sda_pdd0, gen8_i2c_scl_pdd1, + gen8_i2c_sda_pdd2, touch_clk_pdd3, dmic1_clk_pdd4, + dmic1_dat_pdd5, soc_gpio19_pdd6, pwm2_pdd7, + pwm3_pee0, pwm7_pee1, + # drive groups (ordered PAA, PBB, PCC, PDD, PEE) + drive_bootv_ctl_n_paa0, drive_soc_gpio00_paa1, + drive_vcomp_alert_paa2, drive_pwm1_paa3, + drive_batt_oc_paa4, drive_soc_gpio04_paa5, + drive_soc_gpio25_paa6, drive_soc_gpio26_paa7, + drive_hdmi_cec_pbb0, + drive_spi2_sck_pcc0, drive_spi2_miso_pcc1, + drive_spi2_mosi_pcc2, drive_spi2_cs0_pcc3, + drive_spi2_cs1_pcc4, drive_uart3_tx_pcc5, + drive_uart3_rx_pcc6, drive_gen2_i2c_scl_pcc7, + drive_gen2_i2c_sda_pdd0, drive_gen8_i2c_scl_pdd1, + drive_gen8_i2c_sda_pdd2, drive_touch_clk_pdd3, + drive_dmic1_clk_pdd4, drive_dmic1_dat_pdd5, + drive_soc_gpio19_pdd6, drive_pwm2_pdd7, + drive_pwm3_pee0, drive_pwm7_pee1 ] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + pinmux@c300000 { + compatible = "nvidia,tegra238-pinmux-aon"; + reg = <0x0c300000 0x4000>; + + pinctrl-names = "cec"; + pinctrl-0 = <&cec_state>; + + cec_state: pinmux-cec { + cec { + nvidia,pins = "hdmi_cec_pbb0"; + nvidia,function = "hdmi_cec"; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-common.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-common.yaml new file mode 100644 index 000000000000..5c7608981f2d --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-common.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra238-pinmux-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra238 Pinmux Controller + +maintainers: + - Thierry Reding + - Jon Hunter + +$ref: nvidia,tegra-pinmux-common.yaml + +properties: + nvidia,function: + enum: [ dca_vsync, dca_hsync, displaya, rsvd0, i2c7_clk, i2c7_dat, + i2c4_dat, i2c4_clk, i2c9_dat, i2c9_clk, usb_vbus_en0, + usb_vbus_en1, spi3_din, spi1_cs0, spi3_cs0, spi1_din, + spi3_cs1, spi1_sck, spi3_sck, spi1_cs1, spi1_dout, spi3_dout, + gp_pwm5, gp_pwm6, extperiph2_clk, extperiph1_clk, i2c3_dat, + i2c3_clk, extperiph4_clk, extperiph3_clk, dmic2_dat, + dmic2_clk, uarta_cts, uarta_rts, uarta_rxd, uarta_txd, + i2c5_clk, i2c5_dat, uartd_cts, uartd_rts, uartd_rxd, + uartd_txd, i2c1_clk, i2c1_dat, sdmmc1_cd, i2s2_sclk, + i2s2_sdata_out, i2s2_sdata_in, i2s2_lrck, i2s4_sclk, + i2s4_sdata_out, i2s4_sdata_in, i2s4_lrck, i2s1_sclk, + i2s1_sdata_out, i2s1_sdata_in, i2s1_lrck, aud_mclk, + i2s3_lrck, i2s3_sclk, i2s3_sdata_in, i2s3_sdata_out, + pe2_clkreq_l, pe1_clkreq_l, pe1_rst_l, pe0_clkreq_l, + pe0_rst_l, pe2_rst_l, pe3_clkreq_l, pe3_rst_l, + dp_aux_ch0_hpd, qspi0_io0, qspi0_io1, qspi0_sck, qspi0_cs_n, + uartg_cts, uartg_rts, uartg_txd, uartg_rxd, sdmmc1_clk, + sdmmc1_cmd, sdmmc1_comp, sdmmc1_dat3, sdmmc1_dat2, + sdmmc1_dat1, sdmmc1_dat0, ufs0, soc_therm_oc1, hdmi_cec, + gp_pwm4, uartc_rxd, uartc_txd, i2c8_dat, i2c8_clk, + spi2_dout, i2c2_clk, spi2_cs0, i2c2_dat, spi2_sck, spi2_din, + ppc_mode_1, ppc_ready, ppc_mode_2, ppc_cc, ppc_mode_0, + ppc_int_n, uarte_txd, uarte_rxd, uartb_txd, uartb_rxd, + uartb_cts, uartb_rts, uarte_cts, uarte_rts, gp_pwm7, + gp_pwm2, gp_pwm3, gp_pwm1, spi2_cs1, dmic1_clk, dmic1_dat, + rsvd1, dcb_hsync, dcb_vsync, soc_therm_oc4, gp_pwm8, + nv_therm_fan_tach0, wdt_reset_outa, ccla_la_trigger_mux, + dspk1_dat, dspk1_clk, nv_therm_fan_tach1, dspk0_dat, + dspk0_clk, i2s5_sclk, i2s6_lrck, i2s6_sdata_in, i2s6_sclk, + i2s6_sdata_out, i2s5_lrck, i2s5_sdata_out, i2s5_sdata_in, + sdmmc1_pe3_rst_l, sdmmc1_pe3_clkreq_l, touch_clk, + ppc_i2c_dat, wdt_reset_outb, spi5_cs1, ppc_rst_n, + ppc_i2c_clk, spi4_cs1, soc_therm_oc3, spi5_sck, spi5_miso, + spi4_sck, spi4_miso, spi4_cs0, spi4_mosi, spi5_cs0, + spi5_mosi, led_blink, rsvd2, dmic3_clk, dmic3_dat, + dmic4_clk, dmic4_dat, tsc_edge_out0, tsc_edge_out3, + tsc_edge_out1, tsc_edge_out2, dmic5_clk, dmic5_dat, rsvd3, + sdmmc1_wp, tsc_edge_out0a, tsc_edge_out0d, tsc_edge_out0b, + tsc_edge_out0c, soc_therm_oc2 ] + + # out of the common properties, only these are allowed for Tegra238 + nvidia,pins: true + nvidia,pull: true + nvidia,tristate: true + nvidia,schmitt: true + nvidia,enable-input: true + nvidia,open-drain: true + nvidia,lock: true + nvidia,drive-type: true + nvidia,io-hv: true + +required: + - nvidia,pins + +additionalProperties: false + +... diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux.yaml new file mode 100644 index 000000000000..92d276634d76 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux.yaml @@ -0,0 +1,219 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra238-pinmux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra238 Pinmux Controller + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + const: nvidia,tegra238-pinmux + + reg: + maxItems: 1 + +patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra238-pinmux-common.yaml + + properties: + nvidia,pins: + items: + enum: [ gpu_pwr_req_pa0, gp_pwm5_pa1, gp_pwm6_pa2, spi3_sck_pa3, + spi3_miso_pa4, spi3_mosi_pa5, spi3_cs0_pa6, spi3_cs1_pa7, + spi1_sck_pb0, spi1_miso_pb1, spi1_mosi_pb2, spi1_cs0_pb3, + spi1_cs1_pb4, pwr_i2c_scl_pc0, pwr_i2c_sda_pc1, + extperiph1_clk_pc2, extperiph2_clk_pc3, cam_i2c_scl_pc4, + cam_i2c_sda_pc5, soc_gpio23_pc6, soc_gpio24_pc7, + soc_gpio27_pd0, soc_gpio55_pd1, soc_gpio29_pd2, + soc_gpio33_pd3, soc_gpio32_pd4, soc_gpio35_pd5, + soc_gpio37_pd6, soc_gpio56_pd7, uart1_tx_pe0, + uart1_rx_pe1, uart1_rts_pe2, uart1_cts_pe3, + soc_gpio13_pf0, soc_gpio14_pf1, soc_gpio15_pf2, + soc_gpio16_pf3, soc_gpio17_pf4, soc_gpio18_pf5, + soc_gpio20_pf6, soc_gpio21_pf7, soc_gpio22_pg0, + soc_gpio06_pg1, uart4_tx_pg2, uart4_rx_pg3, + uart4_rts_pg4, uart4_cts_pg5, soc_gpio41_pg6, + soc_gpio42_pg7, soc_gpio43_ph0, soc_gpio44_ph1, + gen1_i2c_scl_ph2, gen1_i2c_sda_ph3, cpu_pwr_req_ph4, + soc_gpio07_ph5, dap3_clk_pj0, dap3_dout_pj1, + dap3_din_pj2, dap3_fs_pj3, soc_gpio57_pj4, + soc_gpio58_pj5, soc_gpio59_pj6, soc_gpio60_pj7, + soc_gpio45_pk0, soc_gpio46_pk1, soc_gpio47_pk2, + soc_gpio48_pk3, qspi0_sck_pl0, qspi0_io0_pl1, + qspi0_io1_pl2, qspi0_cs_n_pl3, soc_gpio152_pl4, + soc_gpio153_pl5, soc_gpio154_pl6, soc_gpio155_pl7, + soc_gpio156_pm0, soc_gpio157_pm1, soc_gpio158_pm2, + soc_gpio159_pm3, soc_gpio160_pm4, soc_gpio161_pm5, + soc_gpio162_pm6, uart7_tx_pm7, uart7_rx_pn0, + uart7_rts_pn1, uart7_cts_pn2, soc_gpio167_pp0, + soc_gpio168_pp1, soc_gpio169_pp2, soc_gpio170_pp3, + dap4_sclk_pp4, dap4_dout_pp5, dap4_din_pp6, dap4_fs_pp7, + soc_gpio171_pq0, soc_gpio172_pq1, soc_gpio173_pq2, + soc_gpio61_pr0, soc_gpio62_pr1, soc_gpio63_pr2, + soc_gpio64_pr3, soc_gpio65_pr4, soc_gpio66_pr5, + soc_gpio67_pr6, soc_gpio68_pr7, gen4_i2c_scl_ps0, + gen4_i2c_sda_ps1, soc_gpio75_ps2, gen7_i2c_scl_ps3, + gen7_i2c_sda_ps4, soc_gpio78_ps5, gen9_i2c_scl_ps6, + gen9_i2c_sda_ps7, soc_gpio81_pt0, soc_gpio36_pt1, + soc_gpio53_pt2, soc_gpio38_pt3, soc_gpio40_pt4, + soc_gpio34_pt5, usb_vbus_en0_pt6, usb_vbus_en1_pt7, + sdmmc1_clk_pu0, sdmmc1_cmd_pu1, sdmmc1_dat0_pu2, + sdmmc1_dat1_pu3, sdmmc1_dat2_pu4, sdmmc1_dat3_pu5, + ufs0_ref_clk_pv0, ufs0_rst_n_pv1, pex_l0_clkreq_n_pw0, + pex_l0_rst_n_pw1, pex_l1_clkreq_n_pw2, + pex_l1_rst_n_pw3, pex_l2_clkreq_n_pw4, + pex_l2_rst_n_pw5, pex_l3_clkreq_n_pw6, + pex_l3_rst_n_pw7, pex_wake_n_px0, dp_aux_ch0_hpd_px1, + bootv_ctl_n_paa0, soc_gpio00_paa1, vcomp_alert_paa2, + pwm1_paa3, batt_oc_paa4, soc_gpio04_paa5, + soc_gpio25_paa6, soc_gpio26_paa7, hdmi_cec_pbb0, + spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2, + spi2_cs0_pcc3, spi2_cs1_pcc4, uart3_tx_pcc5, + uart3_rx_pcc6, gen2_i2c_scl_pcc7, gen2_i2c_sda_pdd0, + gen8_i2c_scl_pdd1, gen8_i2c_sda_pdd2, touch_clk_pdd3, + dmic1_clk_pdd4, dmic1_dat_pdd5, soc_gpio19_pdd6, + pwm2_pdd7, pwm3_pee0, pwm7_pee1, soc_gpio49_pee2, + soc_gpio82_pee3, soc_gpio50_pee4, soc_gpio83_pee5, + soc_gpio69_pff0, soc_gpio70_pff1, soc_gpio71_pff2, + soc_gpio72_pff3, soc_gpio73_pff4, soc_gpio74_pff5, + soc_gpio80_pff6, soc_gpio76_pff7, soc_gpio77_pgg0, + soc_gpio84_pgg1, uart2_tx_pgg2, uart2_rx_pgg3, + uart2_rts_pgg4, uart2_cts_pgg5, soc_gpio85_pgg6, + uart5_tx_pgg7, uart5_rx_phh0, uart5_rts_phh1, + uart5_cts_phh2, soc_gpio86_phh3, sdmmc1_comp, + # drive groups + drive_soc_gpio36_pt1, drive_soc_gpio53_pt2, + drive_soc_gpio38_pt3, drive_soc_gpio40_pt4, + drive_soc_gpio75_ps2, drive_soc_gpio81_pt0, + drive_soc_gpio78_ps5, drive_soc_gpio34_pt5, + drive_gen7_i2c_scl_ps3, drive_gen7_i2c_sda_ps4, + drive_gen4_i2c_sda_ps1, drive_gen4_i2c_scl_ps0, + drive_gen9_i2c_sda_ps7, drive_gen9_i2c_scl_ps6, + drive_usb_vbus_en0_pt6, drive_usb_vbus_en1_pt7, + drive_soc_gpio61_pr0, drive_soc_gpio62_pr1, + drive_soc_gpio63_pr2, drive_soc_gpio64_pr3, + drive_soc_gpio65_pr4, drive_soc_gpio66_pr5, + drive_soc_gpio67_pr6, drive_soc_gpio68_pr7, + drive_spi3_miso_pa4, drive_spi1_cs0_pb3, + drive_spi3_cs0_pa6, drive_spi1_miso_pb1, + drive_spi3_cs1_pa7, drive_spi1_sck_pb0, + drive_spi3_sck_pa3, drive_spi1_cs1_pb4, + drive_spi1_mosi_pb2, drive_spi3_mosi_pa5, + drive_gpu_pwr_req_pa0, drive_gp_pwm5_pa1, + drive_gp_pwm6_pa2, drive_extperiph2_clk_pc3, + drive_extperiph1_clk_pc2, drive_cam_i2c_sda_pc5, + drive_cam_i2c_scl_pc4, drive_soc_gpio23_pc6, + drive_soc_gpio24_pc7, drive_soc_gpio27_pd0, + drive_soc_gpio29_pd2, drive_soc_gpio32_pd4, + drive_soc_gpio33_pd3, drive_soc_gpio35_pd5, + drive_soc_gpio37_pd6, drive_soc_gpio56_pd7, + drive_soc_gpio55_pd1, drive_uart1_cts_pe3, + drive_uart1_rts_pe2, drive_uart1_rx_pe1, + drive_uart1_tx_pe0, drive_pwr_i2c_scl_pc0, + drive_pwr_i2c_sda_pc1, drive_cpu_pwr_req_ph4, + drive_uart4_cts_pg5, drive_uart4_rts_pg4, + drive_uart4_rx_pg3, drive_uart4_tx_pg2, + drive_gen1_i2c_scl_ph2, drive_gen1_i2c_sda_ph3, + drive_soc_gpio20_pf6, drive_soc_gpio21_pf7, + drive_soc_gpio22_pg0, drive_soc_gpio13_pf0, + drive_soc_gpio14_pf1, drive_soc_gpio15_pf2, + drive_soc_gpio16_pf3, drive_soc_gpio17_pf4, + drive_soc_gpio18_pf5, drive_soc_gpio41_pg6, + drive_soc_gpio42_pg7, drive_soc_gpio43_ph0, + drive_soc_gpio44_ph1, drive_soc_gpio06_pg1, + drive_soc_gpio07_ph5, drive_dap4_sclk_pp4, + drive_dap4_dout_pp5, drive_dap4_din_pp6, + drive_dap4_fs_pp7, drive_soc_gpio167_pp0, + drive_soc_gpio168_pp1, drive_soc_gpio169_pp2, + drive_soc_gpio170_pp3, drive_soc_gpio171_pq0, + drive_soc_gpio172_pq1, drive_soc_gpio173_pq2, + drive_soc_gpio45_pk0, drive_soc_gpio46_pk1, + drive_soc_gpio47_pk2, drive_soc_gpio48_pk3, + drive_soc_gpio57_pj4, drive_soc_gpio58_pj5, + drive_soc_gpio59_pj6, drive_soc_gpio60_pj7, + drive_dap3_fs_pj3, drive_dap3_clk_pj0, + drive_dap3_din_pj2, drive_dap3_dout_pj1, + drive_pex_l2_clkreq_n_pw4, drive_pex_wake_n_px0, + drive_pex_l1_clkreq_n_pw2, drive_pex_l1_rst_n_pw3, + drive_pex_l0_clkreq_n_pw0, drive_pex_l0_rst_n_pw1, + drive_pex_l2_rst_n_pw5, drive_pex_l3_clkreq_n_pw6, + drive_pex_l3_rst_n_pw7, drive_dp_aux_ch0_hpd_px1, + drive_qspi0_io0_pl1, drive_qspi0_io1_pl2, + drive_qspi0_sck_pl0, drive_qspi0_cs_n_pl3, + drive_soc_gpio156_pm0, drive_soc_gpio155_pl7, + drive_soc_gpio160_pm4, drive_soc_gpio154_pl6, + drive_soc_gpio152_pl4, drive_soc_gpio153_pl5, + drive_soc_gpio161_pm5, drive_soc_gpio162_pm6, + drive_soc_gpio159_pm3, drive_soc_gpio157_pm1, + drive_soc_gpio158_pm2, drive_uart7_cts_pn2, + drive_uart7_rts_pn1, drive_uart7_tx_pm7, + drive_uart7_rx_pn0, drive_sdmmc1_clk_pu0, + drive_sdmmc1_cmd_pu1, drive_sdmmc1_dat3_pu5, + drive_sdmmc1_dat2_pu4, drive_sdmmc1_dat1_pu3, + drive_sdmmc1_dat0_pu2, drive_ufs0_rst_n_pv1, + drive_ufs0_ref_clk_pv0, drive_batt_oc_paa4, + drive_bootv_ctl_n_paa0, drive_vcomp_alert_paa2, + drive_hdmi_cec_pbb0, drive_touch_clk_pdd3, + drive_uart3_rx_pcc6, drive_uart3_tx_pcc5, + drive_gen8_i2c_sda_pdd2, drive_gen8_i2c_scl_pdd1, + drive_spi2_mosi_pcc2, drive_gen2_i2c_scl_pcc7, + drive_spi2_cs0_pcc3, drive_gen2_i2c_sda_pdd0, + drive_spi2_sck_pcc0, drive_spi2_miso_pcc1, + drive_soc_gpio49_pee2, drive_soc_gpio50_pee4, + drive_soc_gpio82_pee3, drive_soc_gpio71_pff2, + drive_soc_gpio76_pff7, drive_soc_gpio74_pff5, + drive_soc_gpio00_paa1, drive_soc_gpio19_pdd6, + drive_soc_gpio86_phh3, drive_soc_gpio72_pff3, + drive_soc_gpio77_pgg0, drive_soc_gpio80_pff6, + drive_soc_gpio84_pgg1, drive_soc_gpio83_pee5, + drive_soc_gpio73_pff4, drive_soc_gpio70_pff1, + drive_soc_gpio04_paa5, drive_soc_gpio85_pgg6, + drive_soc_gpio69_pff0, drive_soc_gpio25_paa6, + drive_soc_gpio26_paa7, drive_uart5_tx_pgg7, + drive_uart5_rx_phh0, drive_uart2_tx_pgg2, + drive_uart2_rx_pgg3, drive_uart2_cts_pgg5, + drive_uart2_rts_pgg4, drive_uart5_cts_phh2, + drive_uart5_rts_phh1, drive_pwm7_pee1, + drive_pwm2_pdd7, drive_pwm3_pee0, drive_pwm1_paa3, + drive_spi2_cs1_pcc4, drive_dmic1_clk_pdd4, + drive_dmic1_dat_pdd5, drive_sdmmc1_comp ] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + pinmux@2430000 { + compatible = "nvidia,tegra238-pinmux"; + reg = <0x2430000 0x17000>; + + pinctrl-names = "pex_rst"; + pinctrl-0 = <&pex_rst_c5_out_state>; + + pex_rst_c5_out_state: pinmux-pex-rst-c5-out { + pexrst { + nvidia,pins = "pex_l3_rst_n_pw7"; + nvidia,schmitt = ; + nvidia,enable-input = ; + nvidia,io-hv = ; + nvidia,tristate = ; + nvidia,pull = ; + }; + }; + }; +... -- cgit v1.2.3 From 30a9d5162f25b4a67209677982ee745070f8b6d6 Mon Sep 17 00:00:00 2001 From: Prathamesh Shete Date: Mon, 27 Apr 2026 13:42:29 +0000 Subject: dt-bindings: pinctrl: Document Tegra264 pin controllers Tegra264 contains three pin controllers. Document their compatible strings and describe the list of pins and functions that they provide. Signed-off-by: Prathamesh Shete Reviewed-by: Krzysztof Kozlowski Reviewed-by: Jon Hunter Signed-off-by: Linus Walleij --- .../pinctrl/nvidia,tegra264-pinmux-aon.yaml | 80 ++++++++++ .../pinctrl/nvidia,tegra264-pinmux-common.yaml | 84 +++++++++++ .../pinctrl/nvidia,tegra264-pinmux-main.yaml | 167 +++++++++++++++++++++ .../pinctrl/nvidia,tegra264-pinmux-uphy.yaml | 78 ++++++++++ 4 files changed, 409 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-aon.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-common.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-uphy.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-aon.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-aon.yaml new file mode 100644 index 000000000000..682e6510ed45 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-aon.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-aon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra264 AON Pinmux Controller + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + const: nvidia,tegra264-pinmux-aon + + reg: + maxItems: 1 + +patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra264-pinmux-common.yaml + + properties: + nvidia,pins: + items: + enum: [ soc_gpio00_paa0, vcomp_alert_paa1, ao_retention_n_paa2, + batt_oc_paa3, bootv_ctl_n_paa4, power_on_paa5, + hdmi_cec_paa6, soc_gpio07_paa7, soc_gpio08_pbb0, + soc_gpio09_pbb1, gen2_i2c_scl_pcc0, gen2_i2c_sda_pcc1, + gen3_i2c_scl_pcc2, gen3_i2c_sda_pcc3, gp_pwm4_pcc4, + uart0_tx_pcc5, uart0_rx_pcc6, spi2_sck_pcc7, + spi2_miso_pdd0, spi2_mosi_pdd1, spi2_cs0_n_pdd2, + soc_gpio21_pdd3, soc_gpio22_pdd4, soc_gpio23_pdd5, + soc_gpio24_pdd6, soc_gpio25_pdd7, soc_gpio26_pee0, + soc_gpio27_pee1, soc_gpio28_pee2, soc_gpio29_pee3, + drive_ao_retention_n_paa2, drive_batt_oc_paa3, + drive_power_on_paa5, drive_vcomp_alert_paa1, + drive_bootv_ctl_n_paa4, drive_soc_gpio00_paa0, + drive_soc_gpio07_paa7, drive_soc_gpio08_pbb0, + drive_soc_gpio09_pbb1, drive_hdmi_cec_paa6, + drive_gen2_i2c_scl_pcc0, drive_gen2_i2c_sda_pcc1, + drive_gen3_i2c_scl_pcc2, drive_gen3_i2c_sda_pcc3, + drive_gp_pwm4_pcc4, drive_uart0_tx_pcc5, + drive_uart0_rx_pcc6, drive_spi2_sck_pcc7, + drive_spi2_miso_pdd0, drive_spi2_mosi_pdd1, + drive_spi2_cs0_n_pdd2, drive_soc_gpio21_pdd3, + drive_soc_gpio22_pdd4, drive_soc_gpio23_pdd5, + drive_soc_gpio24_pdd6, drive_soc_gpio25_pdd7, + drive_soc_gpio26_pee0, drive_soc_gpio27_pee1, + drive_soc_gpio28_pee2, drive_soc_gpio29_pee3 ] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + pinmux@c7a2000 { + compatible = "nvidia,tegra264-pinmux-aon"; + reg = <0xc7a2000 0x2000>; + + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux-default { + uart0 { + nvidia,pins = "uart0_tx_pcc5"; + nvidia,function = "uarta_txd"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-common.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-common.yaml new file mode 100644 index 000000000000..d644c496d8a5 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-common.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra264 Pinmux Common Properties + +maintainers: + - Thierry Reding + - Jon Hunter + +$ref: nvidia,tegra-pinmux-common.yaml + +properties: + nvidia,function: + enum: [ dca_vsync, dca_hsync, rsvd0, dp_aux_ch0_hpd, dp_aux_ch1_hpd, + dp_aux_ch2_hpd, dp_aux_ch3_hpd, gp_pwm2, gp_pwm3, i2c7_clk, + i2c7_dat, i2c9_clk, i2c9_dat, uartk_cts, uartk_rts, uartk_rxd, + uartk_txd, spi3_cs0, spi3_cs3, spi3_din, spi3_dout, spi3_sck, + uartf_cts, uartf_rts, uartf_rxd, uartf_txd, spi1_cs0, spi1_cs1, + spi1_din, spi1_dout, spi1_sck, extperiph2_clk, extperiph1_clk, + i2c12_clk, i2c12_dat, nv_therm_fan_tach0, gp_pwm9, uartj_cts, + uartj_rts, uartj_rxd, uartj_txd, i2c0_clk, i2c0_dat, i2c1_clk, + i2c1_dat, i2s2_lrck, i2s2_sclk, i2s2_sdata_out, i2s2_sdata_in, + gp_pwm10, uarte_cts, uarte_rts, uarte_rxd, uarte_txd, i2c5_dat, + i2c5_clk, i2s6_sdata_in, i2s6_sdata_out, i2s6_lrck, i2s6_sclk, + i2s4_sdata_out, i2s4_sclk, i2s4_sdata_in, i2s4_lrck, spi5_cs0, + spi5_din, spi5_dout, spi5_sck, aud_mclk, i2s1_sclk, i2s1_sdata_in, + i2s1_sdata_out, i2s1_lrck, i2c11_clk, i2c11_dat, xhalt_trig, + gp_pwm1, gp_pwm6, gp_pwm7, gp_pwm8, ufs0, pe1_clkreq_l, pe1_rst_l, + pe2_rst_l, pe2_clkreq_l, pe3_clkreq_l, pe3_rst_l, sgmii0_sma_mdio, + sgmii0_sma_mdc, usb_vbus_en0, usb_vbus_en1, eth1_mdio, pe4_clkreq_l, + pe4_rst_l, pe5_clkreq_l, pe5_rst_l, eth0_mdio, eth0_mdc, eth1_mdc, + eth2_mdio, eth2_mdc, eth3_mdio, eth3_mdc, qspi0_cs_n, qspi0_io0, + qspi0_io1, qspi0_io2, qspi0_io3, qspi0_sck, sdmmc1_clk, sdmmc1_cmd, + sdmmc1_comp, sdmmc1_dat3, sdmmc1_dat2, sdmmc1_dat1, sdmmc1_dat0, + qspi3_sck, qspi3_cs0, qspi3_io0, qspi3_io1, dcb_vsync, dcb_hsync, + dsa_lspii, dce_vsync, dce_hsync, dch_vsync, dch_hsync, bl_en, + bl_pwm_dim0, rsvd1, soc_therm_oc3, i2s5_sclk, i2s5_sdata_in, + extperiph3_clk, extperiph4_clk, i2s5_sdata_out, i2s5_lrck, + sdmmc1_cd, i2s7_sdata_in, spi4_sck, spi4_din, spi4_dout, spi4_cs0, + spi4_cs1, gp_pwm5, i2c14_clk, i2c14_dat, i2s8_sclk, i2s8_sdata_out, + i2s8_lrck, i2s8_sdata_in, i2c16_clk, i2c16_dat, i2s3_sclk, + i2s3_sdata_out, i2s3_sdata_in, i2s3_lrck, pm_trig1, pm_trig0, + qspi2_sck, qspi2_cs0, qspi2_io0, qspi2_io1, dcc_vsync, dcc_hsync, + rsvd2, dcf_vsync, dcf_hsync, soundwire1_clk, soundwire1_dat0, + soundwire1_dat1, soundwire1_dat2, dmic2_clk, dmic2_dat, + nv_therm_fan_tach1, i2c15_clk, i2c15_dat, i2s7_lrck, + ccla_la_trigger_mux, i2s7_sclk, i2s7_sdata_out, dmic1_dat, + dmic1_clk, dcd_vsync, dcd_hsync, rsvd3, dcg_vsync, dcg_hsync, + dspk1_clk, dspk1_dat, soc_therm_oc2, istctrl_ist_done_n, + soc_therm_oc1, tsc_edge_out0c, tsc_edge_out0d, tsc_edge_out0a, + tsc_edge_out0b, touch_clk, hdmi_cec, i2c2_clk, i2c2_dat, i2c3_clk, + i2c3_dat, gp_pwm4, uarta_txd, uarta_rxd, spi2_sck, spi2_din, + spi2_dout, spi2_cs0, tsc_sync1, tsc_edge_out3, tsc_edge_out0, + tsc_edge_out1, tsc_sync0, soundwire0_clk, soundwire0_dat0, + l0l1_rst_out_n, l2_rst_out_n, uartl_txd, uartl_rxd, i2s9_sclk, + i2s9_sdata_out, i2s9_sdata_in, i2s9_lrck, dmic5_dat, dmic5_clk, + tsc_edge_out2 ] + + # out of the common properties, only these are allowed for Tegra264 + nvidia,pins: true + nvidia,pull: true + nvidia,tristate: true + nvidia,schmitt: true + nvidia,enable-input: true + nvidia,open-drain: true + nvidia,lock: true + nvidia,drive-type: true + nvidia,io-hv: true + +required: + - nvidia,pins + +# We would typically use unevaluatedProperties here but that has the +# downside that all the properties in the common bindings become valid +# for all chip generations. In this case, however, we want the per-SoC +# bindings to be able to override which of the common properties are +# allowed, since not all pinmux generations support the same sets of +# properties. This way, the common bindings define the format of the +# properties but the per-SoC bindings define which of them apply to a +# given chip. +additionalProperties: false diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml new file mode 100644 index 000000000000..c40409d3263c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml @@ -0,0 +1,167 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-main.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra264 Main Pinmux Controller + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + const: nvidia,tegra264-pinmux-main + + reg: + maxItems: 1 + +patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra264-pinmux-common.yaml + + properties: + nvidia,pins: + items: + enum: [ pwm1_pa0, pwm6_pa1, pwm7_pa2, pwm8_pa3, ufs0_ref_clk_pa4, + ufs0_rst_n_pa5, soc_gpio250_pf0, soc_gpio251_pf1, + soc_gpio252_pf2, dp_aux_ch0_hpd_pf3, dp_aux_ch1_hpd_pf4, + dp_aux_ch2_hpd_pf5, dp_aux_ch3_hpd_pf6, pwm2_pf7, pwm3_pg0, + gen7_i2c_scl_pg1, gen7_i2c_sda_pg2, gen9_i2c_scl_pg3, + gen9_i2c_sda_pg4, sdmmc1_clk_px0, sdmmc1_cmd_px1, + sdmmc1_dat0_px2, sdmmc1_dat1_px3, sdmmc1_dat2_px4, + sdmmc1_dat3_px5, sdmmc1_comp, soc_gpio124_pl0, + soc_gpio125_pl1, fan_tach0_pl2, soc_gpio127_pl3, + soc_gpio128_pl4, soc_gpio129_pl5, soc_gpio130_pl6, + soc_gpio131_pl7, gp_pwm9_pm0, soc_gpio133_pm1, uart9_tx_pm2, + uart9_rx_pm3, uart9_rts_n_pm4, uart9_cts_n_pm5, + soc_gpio170_pu0, soc_gpio171_pu1, soc_gpio172_pu2, + soc_gpio173_pu3, soc_gpio174_pu4, soc_gpio175_pu5, + soc_gpio176_pu6, soc_gpio177_pu7, soc_gpio178_pv0, + pwm10_pv1, uart4_tx_pv2, uart4_rx_pv3, uart4_rts_n_pv4, + uart4_cts_n_pv5, dap2_clk_pv6, dap2_din_pv7, dap2_dout_pw0, + dap2_fs_pw1, gen1_i2c_scl_pw2, gen1_i2c_sda_pw3, + gen0_i2c_scl_pw4, gen0_i2c_sda_pw5, pwr_i2c_scl_pw6, + pwr_i2c_sda_pw7, soc_gpio138_pp0, soc_gpio139_pp1, + dap6_sclk_pp2, dap6_dout_pp3, dap6_din_pp4, dap6_fs_pp5, + dap4_sclk_pp6, dap4_dout_pp7, dap4_din_pq0, dap4_fs_pq1, + spi5_sck_pq2, spi5_miso_pq3, spi5_mosi_pq4, spi5_cs0_pq5, + soc_gpio152_pq6, soc_gpio153_pq7, aud_mclk_pr0, + soc_gpio155_pr1, dap1_sclk_pr2, dap1_out_pr3, dap1_in_pr4, + dap1_fs_pr5, gen11_i2c_scl_pr6, gen11_i2c_sda_pr7, + soc_gpio350_ps0, soc_gpio351_ps1, qspi0_sck_pt0, + qspi0_cs_n_pt1, qspi0_io0_pt2, qspi0_io1_pt3, qspi0_io2_pt4, + qspi0_io3_pt5, soc_gpio192_pt6, soc_gpio270_py0, + soc_gpio271_py1, soc_gpio272_py2, soc_gpio273_py3, + soc_gpio274_py4, soc_gpio275_py5, soc_gpio276_py6, + soc_gpio277_py7, soc_gpio278_pz0, soc_gpio279_pz1, + xhalt_trig_pz2, soc_gpio281_pz3, soc_gpio282_pz4, + soc_gpio283_pz5, soc_gpio284_pz6, soc_gpio285_pz7, + soc_gpio286_pal0, soc_gpio287_pal1, soc_gpio288_pal2, + cpu_pwr_req_ph0, gpu_pwr_req_ph1, uart10_tx_ph2, + uart10_rx_ph3, uart10_rts_n_ph4, uart10_cts_n_ph5, + spi3_sck_ph6, spi3_miso_ph7, spi3_mosi_pj0, spi3_cs0_pj1, + spi3_cs3_pj2, uart5_tx_pj3, uart5_rx_pj4, uart5_rts_n_pj5, + uart5_cts_n_pj6, spi1_sck_pj7, spi1_miso_pk0, spi1_mosi_pk1, + spi1_cs0_pk2, spi1_cs1_pk3, extperiph1_clk_pk4, + extperiph2_clk_pk5, gen12_i2c_scl_pk6, gen12_i2c_sda_pk7, + drive_cpu_pwr_req_ph0, drive_gpu_pwr_req_ph1, + drive_uart10_cts_n_ph5, drive_uart10_rts_n_ph4, + drive_uart10_rx_ph3, drive_uart10_tx_ph2, + drive_spi3_cs0_pj1, drive_spi3_cs3_pj2, + drive_spi3_miso_ph7, drive_spi3_mosi_pj0, + drive_spi3_sck_ph6, drive_uart5_cts_n_pj6, + drive_uart5_rts_n_pj5, drive_uart5_rx_pj4, + drive_uart5_tx_pj3, drive_spi1_cs0_pk2, + drive_spi1_cs1_pk3, drive_spi1_miso_pk0, + drive_spi1_mosi_pk1, drive_spi1_sck_pj7, + drive_extperiph2_clk_pk5, drive_extperiph1_clk_pk4, + drive_gen12_i2c_scl_pk6, drive_gen12_i2c_sda_pk7, + drive_soc_gpio124_pl0, drive_soc_gpio125_pl1, + drive_fan_tach0_pl2, drive_soc_gpio127_pl3, + drive_soc_gpio128_pl4, drive_soc_gpio129_pl5, + drive_soc_gpio130_pl6, drive_soc_gpio131_pl7, + drive_gp_pwm9_pm0, drive_soc_gpio133_pm1, + drive_uart9_cts_n_pm5, drive_uart9_rts_n_pm4, + drive_uart9_rx_pm3, drive_uart9_tx_pm2, + drive_sdmmc1_clk_px0, drive_sdmmc1_cmd_px1, + drive_sdmmc1_dat3_px5, drive_sdmmc1_dat2_px4, + drive_sdmmc1_dat1_px3, drive_sdmmc1_dat0_px2, + drive_qspi0_cs_n_pt1, drive_qspi0_io0_pt2, + drive_qspi0_io1_pt3, drive_qspi0_io2_pt4, + drive_qspi0_io3_pt5, drive_qspi0_sck_pt0, + drive_soc_gpio192_pt6, drive_soc_gpio138_pp0, + drive_soc_gpio139_pp1, drive_dap6_din_pp4, + drive_dap6_dout_pp3, drive_dap6_fs_pp5, + drive_dap6_sclk_pp2, drive_dap4_dout_pp7, + drive_dap4_sclk_pp6, drive_dap4_din_pq0, + drive_dap4_fs_pq1, drive_spi5_cs0_pq5, + drive_spi5_miso_pq3, drive_spi5_mosi_pq4, + drive_spi5_sck_pq2, drive_soc_gpio152_pq6, + drive_soc_gpio153_pq7, drive_soc_gpio155_pr1, + drive_aud_mclk_pr0, drive_dap1_sclk_pr2, + drive_dap1_in_pr4, drive_dap1_out_pr3, + drive_dap1_fs_pr5, drive_gen11_i2c_scl_pr6, + drive_gen11_i2c_sda_pr7, drive_soc_gpio350_ps0, + drive_soc_gpio351_ps1, drive_gen0_i2c_scl_pw4, + drive_gen0_i2c_sda_pw5, drive_gen1_i2c_scl_pw2, + drive_gen1_i2c_sda_pw3, drive_dap2_fs_pw1, + drive_dap2_clk_pv6, drive_dap2_din_pv7, + drive_dap2_dout_pw0, drive_pwm10_pv1, + drive_soc_gpio170_pu0, drive_soc_gpio171_pu1, + drive_soc_gpio172_pu2, drive_soc_gpio173_pu3, + drive_soc_gpio174_pu4, drive_soc_gpio175_pu5, + drive_soc_gpio176_pu6, drive_soc_gpio177_pu7, + drive_soc_gpio178_pv0, drive_uart4_cts_n_pv5, + drive_uart4_rts_n_pv4, drive_uart4_rx_pv3, + drive_uart4_tx_pv2, drive_pwr_i2c_sda_pw7, + drive_pwr_i2c_scl_pw6, drive_soc_gpio250_pf0, + drive_soc_gpio251_pf1, drive_soc_gpio252_pf2, + drive_dp_aux_ch0_hpd_pf3, drive_dp_aux_ch1_hpd_pf4, + drive_dp_aux_ch2_hpd_pf5, drive_dp_aux_ch3_hpd_pf6, + drive_pwm2_pf7, drive_pwm3_pg0, + drive_gen7_i2c_scl_pg1, drive_gen7_i2c_sda_pg2, + drive_gen9_i2c_scl_pg3, drive_gen9_i2c_sda_pg4, + drive_soc_gpio270_py0, drive_soc_gpio271_py1, + drive_soc_gpio272_py2, drive_soc_gpio273_py3, + drive_soc_gpio274_py4, drive_soc_gpio275_py5, + drive_soc_gpio276_py6, drive_soc_gpio277_py7, + drive_soc_gpio278_pz0, drive_soc_gpio279_pz1, + drive_soc_gpio282_pz4, drive_soc_gpio283_pz5, + drive_soc_gpio284_pz6, drive_soc_gpio285_pz7, + drive_soc_gpio286_pal0, drive_soc_gpio287_pal1, + drive_soc_gpio288_pal2, drive_xhalt_trig_pz2, + drive_soc_gpio281_pz3 ] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + pinmux@c281000 { + compatible = "nvidia,tegra264-pinmux-main"; + reg = <0xc281000 0xc000>; + + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux-default { + sdmmc1 { + nvidia,pins = "sdmmc1_clk_px0"; + nvidia,function = "sdmmc1_cd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-uphy.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-uphy.yaml new file mode 100644 index 000000000000..9a54795d9cc5 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-uphy.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-uphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra264 UPHY Pinmux Controller + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + const: nvidia,tegra264-pinmux-uphy + + reg: + maxItems: 1 + +patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra264-pinmux-common.yaml + + properties: + nvidia,pins: + items: + enum: [ eth1_mdio_pe0, pex_l4_clkreq_n_pd0, pex_l4_rst_n_pd1, + pex_l5_clkreq_n_pd2, pex_l5_rst_n_pd3, eth0_mdio_pd4, + eth0_mdc_pd5, eth1_mdc_pe1, eth2_mdio_pe2, eth2_mdc_pe3, + eth3_mdio_pd6, eth3_mdc_pd7, pex_l1_clkreq_n_pb0, + pex_l1_rst_n_pb1, pex_wake_n_pc2, pex_l2_rst_n_pb3, + pex_l2_clkreq_n_pb2, pex_l3_clkreq_n_pb4, pex_l3_rst_n_pb5, + sgmii0_sma_mdio_pc0, sgmii0_sma_mdc_pc1, soc_gpio113_pb6, + soc_gpio114_pb7, pwm1_pa0, pwm6_pa1, pwm7_pa2, pwm8_pa3, + ufs0_ref_clk_pa4, ufs0_rst_n_pa5, drive_eth1_mdio_pe0, + drive_pex_l4_clkreq_n_pd0, drive_pex_l4_rst_n_pd1, + drive_pex_l5_clkreq_n_pd2, drive_pex_l5_rst_n_pd3, + drive_eth0_mdio_pd4, drive_eth0_mdc_pd5, drive_eth1_mdc_pe1, + drive_eth2_mdio_pe2, drive_eth2_mdc_pe3, drive_eth3_mdio_pd6, + drive_eth3_mdc_pd7, drive_pex_l1_clkreq_n_pb0, + drive_pex_l1_rst_n_pb1, drive_pex_wake_n_pc2, + drive_pex_l2_rst_n_pb3, drive_pex_l2_clkreq_n_pb2, + drive_pex_l3_clkreq_n_pb4, drive_pex_l3_rst_n_pb5, + drive_sgmii0_sma_mdio_pc0, drive_sgmii0_sma_mdc_pc1, + drive_soc_gpio113_pb6, drive_soc_gpio114_pb7, + drive_pwm1_pa0, drive_pwm6_pa1, drive_pwm7_pa2, + drive_pwm8_pa3, drive_ufs0_ref_clk_pa4, drive_ufs0_rst_n_pa5 ] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + pinmux@82e0000 { + compatible = "nvidia,tegra264-pinmux-uphy"; + reg = <0x82e0000 0x4000>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_default>; + + pinmux_default: pinmux-default { + pex { + nvidia,pins = "pex_l1_rst_n_pb1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; -- cgit v1.2.3 From 8c63821f227f7fd8b9e0adc3cd4b26e5b8eeb71e Mon Sep 17 00:00:00 2001 From: Xianwei Zhao Date: Thu, 7 May 2026 08:21:06 +0000 Subject: dt-bindings: pinctl: amlogic,pinctrl-a4: Add compatible string for A9 Update dt-binding document for pinctrl of Amlogic A9. In Amlogic A9 SoC, a bank mux register reuse other banks. The multiplexed part requires special processing and is therefore incompatible with the previous SoCs. Signed-off-by: Xianwei Zhao Acked-by: Conor Dooley Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml index 6ba66c2033b4..b69db1b95345 100644 --- a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml @@ -17,6 +17,7 @@ properties: oneOf: - enum: - amlogic,pinctrl-a4 + - amlogic,pinctrl-a9 - amlogic,pinctrl-s6 - amlogic,pinctrl-s7 - items: -- cgit v1.2.3 From 248ff9624dc09deed69c718c092d78e04d3bda17 Mon Sep 17 00:00:00 2001 From: Luca Leonardo Scorcia Date: Mon, 1 Jun 2026 17:26:42 +0200 Subject: dt-bindings: pinctrl: mediatek: mt6795: document the slew-rate property The driver for MT6795 pinctrl already supports the slew-rate property. Add its description to the documentation. Signed-off-by: Luca Leonardo Scorcia Acked-by: Conor Dooley Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml index 68e91c05f122..9a937f414cc9 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml @@ -152,6 +152,14 @@ patternProperties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1, 2, 3] + slew-rate: + description: | + Set the slew rate. Valid arguments are described as below: + 0: Normal slew rate + 1: Slower slew + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + required: - pinmux -- cgit v1.2.3 From 388d2fe16283d68e4be8c5317809a4a218ebeace Mon Sep 17 00:00:00 2001 From: Yu-Chun Lin Date: Mon, 1 Jun 2026 15:52:29 +0800 Subject: dt-bindings: pinctrl: realtek,rtd1625: Fix input voltage property name The property 'input-voltage-microvolt' is a typo. Rename it to 'input-threshold-voltage-microvolt' to align with the standard pin configuration defined in pincfg-node.yaml and parsed by pinconf-generic.c. Fixes: f6ea7004e926 ("dt-bindings: pinctrl: realtek: Add RTD1625 pinctrl binding") Signed-off-by: Yu-Chun Lin Acked-by: Conor Dooley Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/realtek,rtd1625-pinctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/realtek,rtd1625-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1625-pinctrl.yaml index 9562a043707e..adc5955a2047 100644 --- a/Documentation/devicetree/bindings/pinctrl/realtek,rtd1625-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1625-pinctrl.yaml @@ -110,7 +110,7 @@ patternProperties: input-schmitt-disable: true - input-voltage-microvolt: + input-threshold-voltage-microvolt: description: | Select the input receiver voltage domain for the pin. Valid arguments are: -- cgit v1.2.3 From 11f25ac56372560762ae1cd6f8880d903f6d5825 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 27 Mar 2026 11:30:05 +0000 Subject: dt-bindings: pinctrl: sun55i-a523: increase IRQ banks number The Allwinner A523 SoC implements 10 GPIO banks in the first pinctrl instance, but it skips the first bank (PortA), so their index goes from 1 to 10. The same is actually true for the IRQ banks: there are registers for 11 banks, though the first bank is not implemented (RAZ/WI). In contrast to previous SoCs, the count of the IRQ banks starts with this first unimplemented bank, so we need to provide an interrupt for it. And indeed the A523 user manual lists an interrupt number for PortA, so we need to increase the maximum number of interrupts per pin controller to 11, to be able to assign the correct interrupt number for each bank. Signed-off-by: Andre Przywara Acked-by: Rob Herring (Arm) Reviewed-by: Jernej Skrabec Reviewed-by: Chen-Yu Tsai Signed-off-by: Linus Walleij --- .../bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml index 154e03da8ce9..f87b8274cc37 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml @@ -34,7 +34,7 @@ properties: interrupts: minItems: 2 - maxItems: 10 + maxItems: 11 description: One interrupt per external interrupt bank supported on the controller, sorted by bank number ascending order. @@ -61,7 +61,7 @@ properties: bank found in the controller $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 2 - maxItems: 10 + maxItems: 11 patternProperties: # It's pretty scary, but the basic idea is that: @@ -130,8 +130,8 @@ allOf: then: properties: interrupts: - minItems: 10 - maxItems: 10 + minItems: 11 + maxItems: 11 - if: properties: -- cgit v1.2.3 From 7156d900a22e9240741ba2b182d573239fab7e74 Mon Sep 17 00:00:00 2001 From: Prathamesh Shete Date: Mon, 8 Jun 2026 09:41:21 +0000 Subject: dt-bindings: pinctrl: tegra238: add missing AON pin groups Add 24 pin groups, and their matching drive groups, on ports EE, FF, GG and HH to the Tegra238 AON pinmux binding. These groups are present on the AON pin controller, so device trees that mux these pins through it validate against the schema. Fixes: 9323f8a0e12c ("dt-bindings: pinctrl: Document Tegra238 pin controllers") Signed-off-by: Prathamesh Shete Acked-by: Conor Dooley Signed-off-by: Linus Walleij --- .../pinctrl/nvidia,tegra238-pinmux-aon.yaml | 26 +++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml index ab9264d87c88..2b2e1a82880e 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml @@ -38,8 +38,16 @@ patternProperties: gen2_i2c_sda_pdd0, gen8_i2c_scl_pdd1, gen8_i2c_sda_pdd2, touch_clk_pdd3, dmic1_clk_pdd4, dmic1_dat_pdd5, soc_gpio19_pdd6, pwm2_pdd7, - pwm3_pee0, pwm7_pee1, - # drive groups (ordered PAA, PBB, PCC, PDD, PEE) + pwm3_pee0, pwm7_pee1, soc_gpio49_pee2, + soc_gpio82_pee3, soc_gpio50_pee4, soc_gpio83_pee5, + soc_gpio69_pff0, soc_gpio70_pff1, soc_gpio71_pff2, + soc_gpio72_pff3, soc_gpio73_pff4, soc_gpio74_pff5, + soc_gpio80_pff6, soc_gpio76_pff7, soc_gpio77_pgg0, + soc_gpio84_pgg1, uart2_tx_pgg2, uart2_rx_pgg3, + uart2_rts_pgg4, uart2_cts_pgg5, soc_gpio85_pgg6, + uart5_tx_pgg7, uart5_rx_phh0, uart5_rts_phh1, + uart5_cts_phh2, soc_gpio86_phh3, + # drive groups (ordered PAA, PBB, PCC, PDD, PEE, PFF, PGG, PHH) drive_bootv_ctl_n_paa0, drive_soc_gpio00_paa1, drive_vcomp_alert_paa2, drive_pwm1_paa3, drive_batt_oc_paa4, drive_soc_gpio04_paa5, @@ -53,7 +61,19 @@ patternProperties: drive_gen8_i2c_sda_pdd2, drive_touch_clk_pdd3, drive_dmic1_clk_pdd4, drive_dmic1_dat_pdd5, drive_soc_gpio19_pdd6, drive_pwm2_pdd7, - drive_pwm3_pee0, drive_pwm7_pee1 ] + drive_pwm3_pee0, drive_pwm7_pee1, + drive_soc_gpio49_pee2, drive_soc_gpio50_pee4, + drive_soc_gpio82_pee3, drive_soc_gpio71_pff2, + drive_soc_gpio76_pff7, drive_soc_gpio74_pff5, + drive_soc_gpio86_phh3, drive_soc_gpio72_pff3, + drive_soc_gpio77_pgg0, drive_soc_gpio80_pff6, + drive_soc_gpio84_pgg1, drive_soc_gpio83_pee5, + drive_soc_gpio73_pff4, drive_soc_gpio70_pff1, + drive_soc_gpio85_pgg6, drive_soc_gpio69_pff0, + drive_uart5_tx_pgg7, drive_uart5_rx_phh0, + drive_uart2_tx_pgg2, drive_uart2_rx_pgg3, + drive_uart2_cts_pgg5, drive_uart2_rts_pgg4, + drive_uart5_cts_phh2, drive_uart5_rts_phh1 ] required: - compatible -- cgit v1.2.3 From dac30db978c71af999403f42e4fad68eda5ed09e Mon Sep 17 00:00:00 2001 From: Jia Wang Date: Wed, 10 Jun 2026 13:29:55 +0800 Subject: dt-bindings: pinctrl: Add UltraRISC DP1000 pinctrl controller Add doc for the pinctrl controllers on the UltraRISC DP1000 RISC-V SoC. Signed-off-by: Jia Wang Reviewed-by: Conor Dooley Signed-off-by: Linus Walleij --- .../bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml | 130 +++++++++++++++++++++ 1 file changed, 130 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml new file mode 100644 index 000000000000..c2332e6e60c2 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ultrarisc,dp1000-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UltraRISC DP1000 Pin Controller + +maintainers: + - Jia Wang + +description: | + UltraRISC RISC-V SoC DP1000 pin controller. + The controller manages ports A, B, C, D and LPC. Ports A-D default to + GPIO and provide additional SPI, UART, I2C, and PWM mux functions. + LPC pins default to the LPC interface and can be muxed to eSPI. + All pins also support pin configuration, including drive strength, + pull-up, and pull-down settings. + +properties: + compatible: + const: ultrarisc,dp1000-pinctrl + + reg: + items: + - description: pin controller registers + +required: + - compatible + - reg + +patternProperties: + '.*-pins$': + type: object + unevaluatedProperties: false + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + - if: + properties: + pins: + items: + minimum: 40 + maximum: 52 + then: + properties: + function: + enum: + - lpc + - espi + else: + properties: + pins: + items: + maximum: 39 + function: + enum: + - gpio + - i2c + - pwm + - spi + - uart + + properties: + pins: + description: | + List of pins affected by this state node, using numeric pin IDs. + Pins 0-39 correspond to ports A-D, and pins 40-52 correspond + to LPC0-LPC12. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + uniqueItems: true + items: + minimum: 0 + maximum: 52 + + function: + description: | + Mux function to select for the listed pins. Supported functions + depend on the selected pins and match the DP1000 hardware mux + table. + enum: + - gpio + - i2c + - pwm + - spi + - uart + - lpc + - espi + + bias-disable: true + bias-high-impedance: true + bias-pull-up: true + bias-pull-down: true + + drive-strength: + description: Output drive strength in mA. + enum: [20, 27, 33, 40] + + required: + - pins + - function + +unevaluatedProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl@11081000 { + compatible = "ultrarisc,dp1000-pinctrl"; + reg = <0x0 0x11081000 0x0 0x1000>; + + i2c0-pins { + pins = <12 13>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + uart0-pins { + pins = <8 9>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; + }; + }; -- cgit v1.2.3