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2025-11-14drm/tegra: dsi: Make SOL delay calculation mode independentSvyatoslav Ryhel
Move SOL delay calculation outside of video mode conditions. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://patch.msgid.link/20250909073335.91531-2-clamor95@gmail.com
2025-11-14cxl/region: Remove local variable @inc in cxl_port_setup_targets()Robert Richter
Simplify the code by removing local variable @inc. The variable is not used elsewhere, remove it and directly increment the target number. Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by: Robert Richter <rrichter@amd.com> Link: https://patch.msgid.link/20251114075844.1315805-4-rrichter@amd.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-11-14cxl/acpi: Group xor arithmetric setup code in a single blockRobert Richter
Simplify the xor arithmetric setup code by grouping it in a single block. No need to split the block for QoS setup. It is safe to reorder the call of cxl_setup_extended_linear_cache() because there are no dependencies. Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by: Robert Richter <rrichter@amd.com> Tested-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20251114075844.1315805-3-rrichter@amd.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-11-14cxl: Simplify cxl_rd_ops allocation and handlingRobert Richter
A root decoder's callback handlers are collected in struct cxl_rd_ops. The structure is dynamically allocated, though it contains only a few pointers in it. This also requires to check two pointes to check for the existence of a callback. Simplify the allocation, release and handler check by embedding the ops statically in struct cxl_root_decoder. Implementation is equivalent to how struct cxl_root_ops handles the callbacks. [ dj: Fix spelling error in commit log. ] Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by: Robert Richter <rrichter@amd.com> Link: https://patch.msgid.link/20251114075844.1315805-2-rrichter@amd.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-11-14PCI: cadence: Move PCIe RP common functions to a separate fileManikandan K Pillai
Move the Cadence PCIe controller RP common functions into a separate file. The common library functions are split from legacy PCIe RP controller functions to a separate file. Signed-off-by: Manikandan K Pillai <mpillai@cadence.com> [mani: removed the unused variable] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20251108140305.1120117-4-hans.zhang@cixtech.com
2025-11-14PCI: cadence: Split PCIe controller header fileManikandan K Pillai
Split the Cadence PCIe header file by moving the Legacy (LGA) controller register definitions to a separate header file for support of next generation PCIe controller architecture. Signed-off-by: Manikandan K Pillai <mpillai@cadence.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20251108140305.1120117-3-hans.zhang@cixtech.com
2025-11-14PCI: cadence: Add module support for platform controller driverManikandan K Pillai
Add support for building PCI cadence platforms as a module. Signed-off-by: Manikandan K Pillai <mpillai@cadence.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20251108140305.1120117-2-hans.zhang@cixtech.com
2025-11-14gpu: host1x: Syncpoint interrupt performance optimizationMikko Perttunen
Optimize performance of syncpoint interrupt handling by reading the status register in 64-bit chunks when possible, and skipping processing when the read value is zero. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://patch.msgid.link/20250917-host1x-syncpt-irq-perf-v2-1-736ef69b1347@nvidia.com
2025-11-14Revert "drm/tegra: dsi: Clear enable register if powered by bootloader"Diogo Ivo
Commit b6bcbce33596 ("soc/tegra: pmc: Ensure power-domains are in a known state") was introduced so that all power domains get initialized to a known working state when booting and it does this by shutting them down (including asserting resets and disabling clocks) before registering each power domain with the genpd framework, leaving it to each driver to later on power its needed domains. This caused the Google Pixel C to hang when booting due to a workaround in the DSI driver introduced in commit b22fd0b9639e ("drm/tegra: dsi: Clear enable register if powered by bootloader") meant to handle the case where the bootloader enabled the DSI hardware module. The workaround relies on reading a hardware register to determine the current status and after b6bcbce33596 that now happens in a powered down state thus leading to the boot hang. Fix this by reverting b22fd0b9639e since currently we are guaranteed that the hardware will be fully reset by the time we start enabling the DSI module. Fixes: b6bcbce33596 ("soc/tegra: pmc: Ensure power-domains are in a known state") Cc: stable@vger.kernel.org Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://patch.msgid.link/20251103-diogo-smaug_ec_typec-v1-1-be656ccda391@tecnico.ulisboa.pt
2025-11-14drm/tegra: Add call to put_pid()Prateek Agarwal
Add a call to put_pid() corresponding to get_task_pid(). host1x_memory_context_alloc() does not take ownership of the PID so we need to free it here to avoid leaking. Signed-off-by: Prateek Agarwal <praagarwal@nvidia.com> Fixes: e09db97889ec ("drm/tegra: Support context isolation") [mperttunen@nvidia.com: reword commit message] Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://patch.msgid.link/20250919-host1x-put-pid-v1-1-19c2163dfa87@nvidia.com
2025-11-14drm/xe: Remove duplicate DRM_EXEC selection from KconfigShuicheng Lin
There are 2 identical "select DRM_EXEC" lines for DRM_XE. Remove one to clean up the configuration. Fixes: d490ecf57790 ("drm/xe: Rework xe_exec and the VM rebind worker to use the drm_exec helper") Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Shuicheng Lin <shuicheng.lin@intel.com> Reviewed-by: Nitin Gote <nitin.r.gote@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patch.msgid.link/20251110232657.1807998-2-shuicheng.lin@intel.com Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
2025-11-14drm/tegra: dc: Fix reference leak in tegra_dc_couple()Ma Ke
driver_find_device() calls get_device() to increment the reference count once a matching device is found, but there is no put_device() to balance the reference count. To avoid reference count leakage, add put_device() to decrease the reference count. Found by code review. Cc: stable@vger.kernel.org Fixes: a31500fe7055 ("drm/tegra: dc: Restore coupling of display controllers") Signed-off-by: Ma Ke <make24@iscas.ac.cn> Acked-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://patch.msgid.link/20251022114720.24937-1-make24@iscas.ac.cn
2025-11-14drm/xe/kunit: Fix forcewake assertion in mocs testMatt Roper
The MOCS kunit test calls KUNIT_ASSERT_TRUE_MSG() with a condition of 'true;' this prevents the assertion from ever failing. Replace KUNIT_ASSERT_TRUE_MSG with KUNIT_FAIL_AND_ABORT to get the intended failure behavior in cases where forcewake was not acquired successfully. Fixes: 51c0ee84e4dc ("drm/xe/tests/mocs: Hold XE_FORCEWAKE_ALL for LNCF regs") Cc: Tejas Upadhyay <tejas.upadhyay@intel.com> Cc: Gustavo Sousa <gustavo.sousa@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com> Link: https://patch.msgid.link/20251113234038.2256106-2-matthew.d.roper@intel.com Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
2025-11-14amba: tegra-ahb: Fix device leak on SMMU enableJohan Hovold
Make sure to drop the reference taken to the AHB platform device when looking up its driver data while enabling the SMMU. Note that holding a reference to a device does not prevent its driver data from going away. Fixes: 89c788bab1f0 ("ARM: tegra: Add SMMU enabler in AHB") Cc: stable@vger.kernel.org # 3.5 Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-14soc/tegra: pmc: Document tegra_pmc.syscore fieldThierry Reding
This eliminates a warning from the documentation build targets. Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-14soc/tegra: pmc: Don't fail if "aotag" is not presentPrathamesh Shete
The "aotog" is an optional aperture, so if that aperture is not defined for a given device, then initialise the 'aotag' pointer to NULL instead of returning an error. Note that the PMC driver will not use 'aotag' pointer if initialised to NULL. Co-developed-by: Shardar Mohammed <smohammed@nvidia.com> Signed-off-by: Shardar Mohammed <smohammed@nvidia.com> Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-14Merge tag 'v6.18-p5' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6 Pull crypto fix from Herbert Xu: - Fix device reference leak in hisilicon * tag 'v6.18-p5' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: crypto: hisilicon/qm - Fix device reference leak in qm_get_qos_value
2025-11-14drm/amdgpu: Use amdgpu by default on SI dedicated GPUs (v2)Timur Kristóf
Now that the DC analog connector support and VCE1 support landed, amdgpu is at feature parity with the old radeon driver on SI dGPUs. Enabling the amdgpu driver by default for SI dGPUs has the following benefits: - More stable OpenGL support through RadeonSI - Vulkan support through RADV - Improved performance - Better display features through DC Users who want to keep using the old driver can do so using: amdgpu.si_support=0 radeon.si_support=1 v2: - Update documentation in Kconfig file Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-14drm/amdgpu: Use amdgpu by default on CIK dedicated GPUsTimur Kristóf
The amdgpu driver has been working well on CIK dGPUs for years. Now that the DC analog connector support landed, amdgpu is at feature parity with the old radeon driver on CIK dGPUs. Enabling the amdgpu driver by default for CIK dGPUs has the following benefits: - More stable OpenGL support through RadeonSI - Vulkan support through RADV - Improved performance - Better display features through DC Users who want to keep using the old driver can do so using: amdgpu.cik_support=0 radeon.cik_support=1 v2: - Update documentation in Kconfig file v3: - Rebase documentation updates (Alex) Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-14drm/amdgpu: Fix the issue of missing ras message on sriov hostYiPeng Chai
This code only applies to amdgpu processing poison consumption after uniras is enabled, but not to sriov. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-14drm/amdgpu: Add lock to serialize sriov command executionYiPeng Chai
Add lock to serialize sriov command execution. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-14drm/amdgpu: Synchronize sriov host to add block_mmsch bit fieldYiPeng Chai
Synchronize sriov host to add block_mmsch bit field. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-14drm/amdgpu: use GFP_ATOMIC instead of NOWAIT in the critical pathChristian König
Otherwise job submissions can fail with ENOMEM. We probably need to re-design the per VMID tracking at some point. Signed-off-by: Christian König <christian.koenig@amd.com> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4258 Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-14drm/amdgpu: avoid memory allocation in the critical code path v3Christian König
When we run out of VMIDs we need to wait for some to become available. Previously we were using a dma_fence_array for that, but this means that we have to allocate memory. Instead just wait for the first not signaled fence from the least recently used VMID to signal. That is not as efficient since we end up in this function multiple times again, but allocating memory can easily fail or deadlock if we have to wait for memory to become available. v2: remove now unused VM manager fields v3: fix dma_fence reference Signed-off-by: Christian König <christian.koenig@amd.com> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4258 Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-14drm/amdgpu: Enable xgmi extended peer links for sriov guestWill Aitken
The amd-smi tool relies on extended peer link information to report xgmi link metrics. The necessary xgmi ta command, GET_EXTEND_PEER_LINKS, has been enabled in the host driver and this change is necessary for the guest to make use of it. To handle the case where the host driver does not have the latest xgmi ta, the guest driver checks for guest support through a pf2vf feature flag before invoking psp. Signed-off-by: Will Aitken <wiaitken@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-14drm/amdgpu: Update headers for sriov xgmi ext peer link support feature flagWill Aitken
Adds new sriov msg flag to match host, feature flag in the amdgim enum, and a wrapper macro to check it. Signed-off-by: Will Aitken <wiaitken@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-14drm/amdgpu: Refactor sriov xgmi topology filling to common codeWill Aitken
amdgpu_xgmi_fill_topology_info and psp_xgmi_reflect_topology_info perform the same logic of copying topology info of one node to every other node in the hive. Instead of having two functions that purport to do the same thing, this refactoring moves the logic of the fill function to the reflect function and adds reflecting port number info as well for complete functionality. Signed-off-by: Will Aitken <wiaitken@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-14drm/amdgpu: Use amdgpu by default on CIK dedicated GPUsTimur Kristóf
The amdgpu driver has been working well on CIK dGPUs for years. Now that the DC analog connector support landed, these GPUs are at feature parity with the old radeon driver. Additionally, amdgpu yields extra performance, supports Vulkan and provides more display features through DC as well as more robust power management. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-14drm/amdgpu: Refactor how SI and CIK support is determinedTimur Kristóf
Move the determination into a separate function. Change amdgpu.si_support and amdgpu.cik_support so that their default value is -1 (default). This prepares the code for changing the default driver based on the chip. Also adjust the module param documentation. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-14drm/radeon: Refactor how SI and CIK support is determinedTimur Kristóf
Move the determination into a separate function. Change radeon.si_support and radeon.cik_support so that their default value is -1 (default). This prepares the code for changing the default driver based on the chip. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-14drm/amdgpu: Avoid xgmi register accessLijo Lazar
On single GPU systems, avoid accesses to XGMI link registers. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-14ASoC: codecs: lpass-macro: complete sm6115 supportMark Brown
Merge series from Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>: This patch series fixes SM6115 lpass codec macro support and adding missing dt-bindings to complete support for SM6115. SM6115 lpass codec macro support is added partially and broken to some extent, Fix this broken support and add complete lpass macro support for this SoC.
2025-11-14soc/tegra: fuse: speedo-tegra210: Add SoC speedo 2Aaron Kling
The Jetson Nano series of modules only have 2 EMC table entries, different from other SoC SKUs. As the EMC driver uses the SoC speedo ID to populate the EMC OPP tables, add a new speedo ID to uniquely identify this. Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-14soc/tegra: fuse: speedo-tegra210: Update speedo IDsAaron Kling
Existing code only sets CPU and GPU speedo IDs 0 and 1. The CPU DVFS code supports 11 IDs and nouveau supports 5. This aligns with what the downstream vendor kernel supports. Align SKUs with the downstream list. The Tegra210 CVB tables were added in the first referenced fixes commit. Since then, all Tegra210 SoCs have tried to scale to 1.9 GHz, when the supported devkits are only supposed to scale to 1.5 or 1.7 GHZ. Overclocking should not be the default state. Fixes: 2b2dbc2f94e5 ("clk: tegra: dfll: add CVB tables for Tegra210") Fixes: 579db6e5d9b8 ("arm64: tegra: Enable DFLL support on Jetson Nano") Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-14drm/xe/pf: Fix kernel-doc warning in migration_save_consumeMichał Winiarski
The kernel-doc for xe_sriov_pf_migration_save_consume() contained multiple "Return:" sections, causing a warning. Fix it by removing the extra line. Fixes: 67df4a5cbc583 ("drm/xe/pf: Add data structures and handlers for migration rings") Signed-off-by: Michał Winiarski <michal.winiarski@intel.com> Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patch.msgid.link/20251114134030.1795947-1-michal.winiarski@intel.com Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
2025-11-14Add support for Microchip CoreSPI ControllerMark Brown
Merge series from Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>: This patch series adds support for the Microchip FPGA CoreSPI "soft" IP and documents its device tree bindings. As preparation, the existing Microchip SPI driver is renamed to clearly indicate that it supports only the Microchip PolarFire SoC "hard" controller. Although it was originally named with the expectation that it might also cover the FPGA CoreSPI "soft" IP, the register layouts differ significantly, so separate drivers are required.
2025-11-14ps3disk: use memcpy_{from,to}_bvec indexRene Rebe
With 6e0a48552b8c (ps3disk: use memcpy_{from,to}_bvec) converting ps3disk to new bvec helpers, incrementing the offset was accidently lost, corrupting consecutive buffers. Restore index for non-corrupted data transfers. Fixes: 6e0a48552b8c (ps3disk: use memcpy_{from,to}_bvec) Signed-off-by: René Rebe <rene@exactco.de> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Jens Axboe <axboe@kernel.dk>
2025-11-14usb: sl811-hcd: Add PM_EVENT_POWEROFF into suspend callbacksMario Limonciello (AMD)
When the PM core uses hibernation callbacks for shutdown drivers will receive PM_EVENT_POWEROFF and should handle it the same as PM_EVENT_HIBERNATE would have been used. Tested-by: Eric Naim <dnaim@cachyos.org> Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> [ rjw: Changelog adjustment ] Link: https://patch.msgid.link/20251112224025.2051702-4-superm1@kernel.org Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2025-11-14scsi: Add PM_EVENT_POWEROFF into suspend callbacksMario Limonciello (AMD)
If the PM core uses hibernation callbacks for powering off the system, drivers will receive PM_EVENT_POWEROFF and should handle it the same as they previously handled PM_EVENT_HIBERNATE. Support this case in the scsi driver. No functional changes. Reviewed-by: Martin K. Petersen <martin.petersen@oracle.com> Tested-by: Eric Naim <dnaim@cachyos.org> Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Link: https://patch.msgid.link/20251112224025.2051702-3-superm1@kernel.org Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2025-11-14PM: Introduce new PMSG_POWEROFF eventMario Limonciello (AMD)
PMSG_POWEROFF will be used for the PM core to allow differentiating between a hibernation or shutdown sequence when re-using callbacks for common code. Hibernation is started by writing a hibernation method (such as 'platform' 'shutdown', or 'reboot') to use into /sys/power/disk and writing 'disk' to /sys/power/state. Shutdown is initiated with the reboot() syscall with arguments on whether to halt the system or power it off. Tested-by: Eric Naim <dnaim@cachyos.org> Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Link: https://patch.msgid.link/20251112224025.2051702-2-superm1@kernel.org Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2025-11-14Merge back earlier runtime PM changes for 6.19Rafael J. Wysocki
2025-11-14irqchip/riscv-intc: Add missing free() callback in riscv_intc_domain_opsNick Hu
The irq_domain_free_irqs() helper requires that the irq_domain_ops->free callback is implemented. Otherwise, the kernel reports the warning message "NULL pointer, cannot free irq" when irq_dispose_mapping() is invoked to release the per-HART local interrupts. Set irq_domain_ops->free to irq_domain_free_irqs_top() to cure that. Fixes: 832f15f42646 ("RISC-V: Treat IPIs as normal Linux IRQs") Signed-off-by: Nick Hu <nick.hu@sifive.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://patch.msgid.link/20251114-rv-intc-fix-v1-1-a3edd1c1a868@sifive.com
2025-11-14soc/tegra: Resolve a spelling error in the tegra194-cbb.cBruno Sobreira França
Fix a typo spotted during code reading. Signed-off-by: Bruno Sobreira França <brunofrancadevsec@gmail.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Reviewed-by: Herve Codina <herve.codina@bootlin.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-14soc/tegra: fuse: Do not register SoC device on ACPI bootKartik Rajput
On Tegra platforms using ACPI, the SMCCC driver already registers the SoC device. This makes the registration performed by the Tegra fuse driver redundant. When booted via ACPI, skip registering the SoC device and suppress printing SKU information from the Tegra fuse driver, as this information is already provided by the SMCCC driver. Fixes: 972167c69080 ("soc/tegra: fuse: Add ACPI support for Tegra194 and Tegra234") Cc: stable@vger.kernel.org Signed-off-by: Kartik Rajput <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-14drm/msm/disp: fix kernel-doc warningsRandy Dunlap
Fix all kernel-doc warnings in msm_disp_snapshot.h: msm_disp_snapshot.h:53: warning: Function parameter or struct member 'blocks' not described in 'msm_disp_state' msm_disp_snapshot.h:69: warning: Function parameter or struct member 'node' not described in 'msm_disp_state_block' msm_disp_snapshot.h:69: warning: Excess struct member 'drm_dev' description in 'msm_disp_state_block' msm_disp_snapshot.h:95: warning: No description found for return value of 'msm_disp_snapshot_state_sync' msm_disp_snapshot.h:100: warning: bad line: msm_disp_snapshot.h:117: warning: bad line: msm_disp_snapshot.h:125: warning: bad line: msm_disp_snapshot.h:142: warning: Excess function parameter 'name' description in 'msm_disp_snapshot_add_block' Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/687132/ Link: https://lore.kernel.org/r/20251111060353.1972869-1-rdunlap@infradead.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-11-14drm/msm: mdss: Add QCS8300 supportYongxing Mou
Add Mobile Display Subsystem (MDSS) support for the QCS8300 platform. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/684205/ Link: https://lore.kernel.org/r/20251029-qcs8300_mdss-v13-5-e8c8c4f82da2@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-11-14drm/msm/dp: Add support for GlymurAbel Vesa
The Qualcomm Glymur platform comes with 4 DisplayPort controllers, which have a different core revision compared to all previous platforms. Describe them and add the compatible. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/683722/ Link: https://lore.kernel.org/r/20251027-glymur-display-v3-6-aa13055818ac@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-11-14drm/msm/dpu: Add support for GlymurAbel Vesa
Add DPU version v12.2 support for the Glymur platform. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/683721/ Link: https://lore.kernel.org/r/20251027-glymur-display-v3-5-aa13055818ac@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-11-14drm/msm/mdss: Add Glymur device configurationAbel Vesa
Add Mobile Display Subsystem (MDSS) support for the Glymur platform. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/683718/ Link: https://lore.kernel.org/r/20251027-glymur-display-v3-4-aa13055818ac@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-11-14drm/msm/dpu: drop dpu_hw_dsc_destroy() prototypeDmitry Baryshkov
The commit a106ed98af68 ("drm/msm/dpu: use devres-managed allocation for HW blocks") dropped all dpu_hw_foo_destroy() functions, but the prototype for dpu_hw_dsc_destroy() was omitted. Drop it now to clean up the header. Fixes: a106ed98af68 ("drm/msm/dpu: use devres-managed allocation for HW blocks") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Jessica Zhang <jesszhan0024@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/683697/ Link: https://lore.kernel.org/r/20251027-dpu-drop-dsc-destroy-v1-1-968128de4bf6@oss.qualcomm.com
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