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2026-06-03drm/amd/display: add HDMI 2.1 DSC over FRL supportHarry Wentland
Add all the bits to enable DSC over FRL. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: add HDMI 2.1 Compliance SupportFangzhi Zuo
Add force yuv format from igt for compliance test. Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Tie FRL support into amdgpu_dmHarry Wentland
Tie FRL support into amdgpu_dm, including the FRL status polling workqueue. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Update HDCP and info_packet modules for FRLHarry Wentland
The HDCP module has a minor update for FRL, and info_packet is updated for ALLM. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Add support for FRL to DC coreHarry Wentland
Here we add support for reading BIOS caps and tie FRL bits into the rest of DC core. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Add DC link support for FRLHarry Wentland
Start bringing in the protocol layer for FRL in DC link. This includes FRL training, timing validation, and other protocol bits. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Add DC resource support for FRLHarry Wentland
Add support for FRL in DC resources. This is mostly the register macros, encoder creation, and HW capabilities. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Tie FRL programming together in HWSSHarry Wentland
This patch adds HW Sequencer support for FRL programming, which ties the HW programming for the different blocks together for FRL. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Add FRL support to clk_mgr, dsc, hdcpHarry Wentland
This adds a few, relatively minor, changes for FRL to clk_mgr, DSC, and HDCP blocks. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Add DCCG DIO, HPO, OPP, and OPTC support for FRLHarry Wentland
This adds support to HW block programming for the core blocks for HDMI FRL: - DIO - HPO - OPP - OPTC Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: add HDMI 2.1 FRL base support to DML 2.0Harry Wentland
Add HDMI FRL bits to DML 2.0 Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Add DML changes to support HDMI FRLHarry Wentland
This adds DML support for HDMI FRL. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Add HDMI FRL definitions to includesHarry Wentland
This patch adds all relevant includes in DC that are used by the HDMI FRL implementation in DC. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Fangzhi Zuo <Jerry.Zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Promote DC to 3.2.384Taimur Hassan
This version brings along the following updates: - Enable DCN 4.2.1: * Add register header files for DCN42B * Add DCN42B DC resource files * Add DCN42B DMUB support * Add DCN42B code to DC and dcn42b_soc_bb to DML2 * Add DCN42 PMO init_for_pstate_support * Enable DCN42 PMO policy and pstate pmo * Enable DCN 4.2.1 in amdgpu_dm * Enable DM for DCN 4.2.1 - Add no_native_i2c codepath - Add amdgpu_dm KUnit tests for: * amdgpu_dm_psr_set_event * dm_ism_dispatch_next_event and additional ISM functions * amdgpu_dm_colorop * color LUT functions and transfer function helpers - Enable gcov coverage for amdgpu_dm KUnit builds - Extract dm_ism_dispatch_next_event and transfer function helpers - Refactor amdgpu_dm_initialize_default_pipeline - Clean up PSR helper functions - Fix gamma 2.2 colorop TF direction in tests - Handle aux_inst for connectors without DDC pin - Fix DP_PIXEL_FORMAT fields & update clk_src for DCN4x - Avoid DPMS-on for phantom stream - Change default driver setting for "Force ODM2:1 for eDP" policy - Add DC_VALIDATE_MODE_AND_PROGRAMMING condition check for force odm2:1 - Check for sharpening case when calculating max vtaps for scaler - Add DRAM table fields to clk_mgr_internal - Enable frame skipping in 0x37B - Bound VBIOS record-chain walk loops - Clamp HDMI HDCP2 rx_id_list read to buffer size - Clamp VBIOS HDMI retimer register count to array size - Reject gpio_bitshift >= 32 in bios_parser_get_gpio_pin_info() - Use krealloc_array() in dal_vector_reserve() - Fix NULL deref and buffer over-read in SDP debugfs - Fix out-of-bounds read in dp_get_eq_aux_rd_interval() - FW Release 0.1.61.0 Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03ddrm/amd/display: [FW Promotion] Release 0.1.61.0Taimur Hassan
[Why & How] Update DMUB related command structure. Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Enable DM for DCN 4.2.1Matthew Stewart
[Why & How] Add DM IP block to amdgpu_discovery Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Enable DCN 4.2.1 in amdgpu_dmMatthew Stewart
[Why & How] Add checks for IP version 4.2.1. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Add DCN42B DMUB supportMatthew Stewart
[Why & How] Add DMUB support for DCN42B Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Add DCN42B code to DCMatthew Stewart
[Why & How] Add DCN42B code to DC Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Add dcn42b_soc_bb to DML2Matthew Stewart
[Why & How] Add bounding box for dcn42b Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Add DCN42B DC resource filesMatthew Stewart
[Why & How] Add DC resource files for DCN42B. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd: Add register header files for DCN42BMatthew Stewart
[Why & How] Add register headers for: - clk 15.0.5 - dcn 4.2.1 - dpcs 4.0.1 - nbio 7.15.5 v2: add in missing license (Alex) Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Handle aux_inst for connectors without DDC pinGabe Teeger
[Why & How] Must use an alternative codepath to access AUX channel when link->no_ddc_pin is set. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Add no_native_i2c codepathMatthew Stewart
[Why] ASICs which do not have native DDC capability must use a different codepath to access the AUX channel. [How] - BIOS cap NO_DDC_PIN is set to 1 for links which do not have the DDC pin. - dp_connector_no_native_i2c in dc_config must also be set to true to use this codepath. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Clean up PSR helper functionsAlex Hung
[Why & How] Use the existing local dc variable in amdgpu_dm_set_psr_caps() instead of redundantly dereferencing link->ctx->dc. Simplify amdgpu_dm_psr_is_active_allowed() by replacing with early return and inlining the intermediate stream variable. No functional changes. Assisted-by: Copilot:Claude-Sonnet-4.6 Reviewed-by: Ray Wu <ray.wu@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Export symbols for KUnit test modulesAlex Hung
Add missing EXPORT_IF_KUNIT() calls for amdgpu_dm_psr_set_event, amdgpu_dm_ism_init, and amdgpu_dm_ism_fini so that the KUnit test modules can resolve these symbols when built as modules, i.e., CONFIG_DRM_AMD_DC_KUNIT_TEST=m. Fixes: 34f281489976 ("drm/amd/display: Add KUnit tests for amdgpu_dm_psr_set_event") Fixes: a3142b13fe9f ("drm/amd/display: Add more KUnit tests for amdgpu_dm_ism") Assisted-by: Copilot:Claude-Opus-4.6 Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Add KUnit tests for amdgpu_dm_psr_set_eventAlex Hung
[Why & How] Add three KUnit tests covering the early-exit validation guard in amdgpu_dm_psr_set_event(): - NULL stream argument returns false immediately - Valid stream with NULL link returns false - Valid stream/link with psr_feature_enabled == false returns false Assisted-by: Copilot:Claude-Sonnet-4.6 Reviewed-by: Ray Wu <ray.wu@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Add KUnit tests for dm_ism_dispatch_next_eventAlex Hung
[Why & How] Add 6 KUnit test cases exercising the new helper: - hyst_wait_no_delay: HYSTERESIS_WAITING + delay_ns==0 returns IMMEDIATE (covers null stream / no hysteresis config). - hyst_wait_with_delay: HYSTERESIS_WAITING + delay_ns>0 returns DM_ISM_NUM_EVENTS (timer scheduled, no immediate event). - opt_idle_no_sso_delay: OPTIMIZED_IDLE + sso_delay_ns==0 returns IMMEDIATE (skip SSO, transition immediately). - opt_idle_with_sso_delay: OPTIMIZED_IDLE + sso_delay_ns>0 returns DM_ISM_NUM_EVENTS (SSO timer scheduled). - timer_aborted: TIMER_ABORTED always returns IMMEDIATE regardless of delay values. - no_action_state: all other states return DM_ISM_NUM_EVENTS. Assisted-by: Copilot:Claude-Sonnet-4.6 Reviewed-by: Ray Wu <ray.wu@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Extract dm_ism_dispatch_next_eventAlex Hung
[Why & How] Separate the "should we emit IMMEDIATE?" decision into a pure, side-effect-free helper so it can be tested in isolation without a full DRM context. - dm_ism_dispatch_next_event(current_state, delay_ns, sso_delay_ns) returns DM_ISM_EVENT_IMMEDIATE when the state requires an immediate follow-up (HYSTERESIS_WAITING with zero delay, OPTIMIZED_IDLE with zero SSO delay, or TIMER_ABORTED), and DM_ISM_NUM_EVENTS otherwise. - Removes the passthrough event parameter that was always DM_ISM_NUM_EVENTS at the call site, making the sentinel explicit. - Drops the now-unused event parameter from dm_ism_dispatch_power_state. Assisted-by: Copilot:Claude-Sonnet-4.6 Reviewed-by: Ray Wu <ray.wu@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Add more KUnit tests for amdgpu_dm_ismAlex Hung
[Why & How] Add 8 more KUnit tests: - dm_ism_get_idle_allow_delay: add a case where filter_entry_count exceeds filter_history_size, exercising the max() branch in the history_size calculation. - amdgpu_dm_ism_init: verify all fields are initialised to expected values after construction. - amdgpu_dm_ism_fini: smoke-test cancellation of never-scheduled delayed work items paired with a preceding init. - dm_ism_set_last_idle_ts: verify last_idle_timestamp_ns is updated to at least the value captured before the call. - dm_ism_insert_record: verify index increment and duration calculation; verify out-of-bounds index wraps to slot 0. - dm_ism_trigger_event: verify current_state and previous_state are updated on a valid transition and left unchanged on an invalid one. Assisted-by: Copilot:Claude-Sonnet-4.6 Reviewed-by: Ray Wu <ray.wu@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Add KUnit tests for amdgpu_dm_coloropAlex Hung
[Why & How] Add a KUnit pipeline test for amdgpu_dm_build_default_pipeline(). The pipeline test uses a mock drm_device (via DRM KUnit helpers), calls amdgpu_dm_build_default_pipeline() with hw_3d_lut=true, then walks the returned colorop chain asserting the correct type sequence (degam_tf, mult, ctm, shaper_tf, shaper_lut, 3dlut, blnd_tf, blnd_lut), that every op carries bypass_property, and that the chain length is exactly eight. A kunit cleanup action calls drm_colorop_pipeline_destroy() before the device is torn down. Assisted-by: Copilot:Claude-Sonnet-4.6 Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Fix gamma 2.2 colorop TF direction in testsAlex Hung
[Why & How] Correct the gamma 2.2 TF direction used in the supported-TF bitmask tests. Degam and blnd use DRM_COLOROP_1D_CURVE_GAMMA22 (EOTF direction); shaper uses DRM_COLOROP_1D_CURVE_GAMMA22_INV (inverse EOTF direction). This aligns the tests with commit d8f9f42effd7 ("drm/amd/display: Fix gamma 2.2 colorop TFs"). Assisted-by: Copilot:Claude-Sonnet-4.6 Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Refactor amdgpu_dm_initialize_default_pipelineAlex Hung
[Why & How] Extract amdgpu_dm_initialize_default_pipeline() into a new STATIC_IFN_KUNIT helper amdgpu_dm_build_default_pipeline(). This separation makes the pipeline-building logic testable via KUnit without pulling in amdgpu_device and its dependencies that are unavailable in the UML KUnit build environment. Assisted-by: Copilot:Claude-Sonnet-4.6 Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Add more color KUnit testsAlex Hung
[Why & How] Add KUnit tests for __set_tf_bypass(), __set_tf_distributed_points(), the bypass paths of amdgpu_dm_set_atomic_regamma(), amdgpu_dm_atomic_shaper_lut(), and amdgpu_dm_atomic_blend_lut(), and all three input branches of __set_colorop_in_tf_1d_curve(). Export the three shaper/blend/regamma helpers and __set_colorop_in_tf_1d_curve with STATIC_IFN_KUNIT and EXPORT_IF_KUNIT to make their branches reachable from tests. Add the following test cases in amdgpu_dm_color_test.c: - dm_test_set_tf_bypass: verify bypass TF setup - dm_test_set_tf_distributed_points_srgb: validate sRGB gamma - dm_test_set_tf_distributed_points_pq: validate PQ gamma - dm_test_set_atomic_regamma_bypass: verify regamma bypass path - dm_test_atomic_shaper_lut_bypass: verify shaper LUT bypass path - dm_test_atomic_blend_lut_bypass: verify blend LUT bypass path - dm_test_set_colorop_in_tf_1d_curve_invalid_type: verify invalid colorop type returns -EINVAL - dm_test_set_colorop_in_tf_1d_curve_unsupported_curve: verify unsupported curve type returns -EINVAL - dm_test_set_colorop_in_tf_1d_curve_bypass: verify bypass path sets TF_TYPE_BYPASS and TRANSFER_FUNCTION_LINEAR Assisted-by: Copilot:Claude-Sonnet-4.6 Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Extract transfer function helpersAlex Hung
[Why] Extract repeated inline dc_transfer_func setup patterns into two small helper functions in amdgpu_dm_color.c. Three functions (amdgpu_dm_set_atomic_regamma, amdgpu_dm_atomic_shaper_lut, amdgpu_dm_atomic_blend_lut) each contained identical two-line bypass setup and identical three-line distributed-points setup. __set_colorop_in_tf_1d_curve contained the same two-line bypass pattern as well. [How] Extract to __set_tf_bypass() and __set_tf_distributed_points(). Replace all four bypass sites with __set_tf_bypass(), and all three distributed-points sites with __set_tf_distributed_points(). Assisted-by: Copilot:Claude-Sonnet-4.6 Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Add KUnit tests for color LUT functionsAlex Hung
[Why] Add KUnit tests for three color management functions in amdgpu_dm_color.c: amdgpu_dm_verify_lut_sizes, amdgpu_dm_atomic_lut3d, and __set_colorop_3dlut. [How] Export amdgpu_dm_verify_lut_sizes with EXPORT_IF_KUNIT. Change amdgpu_dm_atomic_lut3d and __set_colorop_3dlut from static to STATIC_IFN_KUNIT and export them with EXPORT_IF_KUNIT. Add their prototypes to amdgpu_dm_color.h inside the KUnit guard block. Implement 14 test cases in amdgpu_dm_color_test.c: - 8 tests for amdgpu_dm_verify_lut_sizes covering null LUTs, valid and invalid degamma/gamma sizes, both valid, and priority - 3 tests for amdgpu_dm_atomic_lut3d covering zero size clearing initialized state, nonzero setting state bits and mode flags, and LUT data forwarding to tetrahedral_17 - 3 tests for __set_colorop_3dlut covering zero size returning -EINVAL and clearing initialized state, nonzero returning 0 and setting state bits, and 32-bit LUT data forwarding to tetrahedral_17 Assisted-by: Copilot:Claude-Sonnet-4.6 Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Fix DP_PIXEL_FORMAT fields & update clk_src for DCN4xOvidiu Bunea
[Why & How] The enc1_stream_encoder_dp_get_pixel_format() function reads fields of the DP_PIXEL_FORMAT register that are deprecated on DCN4x. This breaks seamless boot because driver cannot properly determine the pixel format programmed by VBIOS. The previous changed submitted for this issue incorrectly calculated the DP DTO frequency because register access to DCN4x DP DTO registers was not working. Create a new function that reads the correct fields. Update clk_src structs to support register access for new DCN4x registers & fields. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Bound VBIOS record-chain walk loopsHarry Wentland
[Why & How] All record-chain walk loops in bios_parser.c and bios_parser2.c use for(;;) and only terminate on a 0xFF record_type sentinel or zero record_size. A malformed VBIOS image missing the terminator record causes unbounded iteration at probe time, potentially hundreds of thousands of iterations with record_size=1. In the final iterations near the BIOS image boundary, struct casts beyond the 2-byte header validated by GET_IMAGE can also read out of bounds. Cap all 14 record-chain walk loops to BIOS_MAX_NUM_RECORD (256) iterations. The atombios.h defines up to 22 distinct record types and atomfirmware.h has 13. Assuming an average of less than 10 records per type (which is reasonable since most are connector- based) 256 is a generous upper bound. Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)") Assisted-by: Copilot:claude-opus-4.6 Mythos Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Clamp HDMI HDCP2 rx_id_list read to buffer sizeHarry Wentland
[Why & How] During HDCP 2.x repeater authentication over HDMI, the driver reads the sink's RxStatus register and extracts a 10-bit message size field (max value 1023). This value is used as the read length for the ReceiverID list without being clamped to the size of the destination buffer rx_id_list[177]. A malicious HDMI repeater could advertise a message size larger than the buffer, causing an out-of-bounds write during the I2C read. Clamp the read length in mod_hdcp_read_rx_id_list() to the size of the rx_id_list buffer, matching the approach already used in the DP branch. Fixes: eff682f83c9c ("drm/amd/display: Add DDC handles for HDCP2.2") Assisted-by: Copilot:claude-opus-4.6 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Reject gpio_bitshift >= 32 in bios_parser_get_gpio_pin_info()Harry Wentland
[Why & How] gpio_bitshift is a uint8_t read directly from the VBIOS GPIO pin table. If the value is >= 32, the expression "1 << gpio_bitshift" triggers undefined behaviour in C (shift count exceeds type width). On x86 the shift is silently masked to 5 bits, producing an incorrect GPIO mask that may cause wrong MMIO register bits to be toggled. Validate gpio_bitshift before use and return BP_RESULT_BADBIOSTABLE for out-of-range values. Fixes: ae79c310b1a6 ("drm/amd/display: Add DCE12 bios parser support") Assisted-by: Copilot:claude-opus-4.6 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Use krealloc_array() in dal_vector_reserve()Harry Wentland
[Why & How] dal_vector_reserve() computes the allocation size as "capacity * vector->struct_size" using uint32_t arithmetic, which can silently wrap to a small value on overflow. This would cause krealloc to return a smaller buffer than expected, leading to heap overflows on subsequent vector appends. Replace krealloc() with krealloc_array() which performs an internal overflow check and returns NULL on wrap, preventing the issue. Fixes: 2004f45ef83f ("drm/amd/display: Use kernel alloc/free") Assisted-by: Copilot:claude-opus-4.6 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Fix NULL deref and buffer over-read in SDP debugfsHarry Wentland
[Why & How] dp_sdp_message_debugfs_write() dereferences connector->base.state->crtc without checking for NULL. A connector can be connected but not bound to any CRTC (e.g. after hot-plug before the next atomic commit), causing a kernel crash when writing to the sdp_message debugfs node. The function also ignores the user-provided size argument and always passes 36 bytes to copy_from_user(), reading past the user buffer when size < 36. Fix both issues by: - Returning -ENODEV when connector->base.state or state->crtc is NULL - Clamping write_size to min(size, sizeof(data)) Fixes: c7ba3653e977 ("drm/amd/display: Generic SDP message access in amdgpu") Assisted-by: Copilot:claude-opus-4.6 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Avoid DPMS-on for phantom streamIlya Bakoulin
[Why & How] Calling dc_update_planes_and_stream separately for stream and its phantom stream causes a NULL pointer dereference, since the phantom is destroyed on the first call. Skip the call for phantom streams. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Clamp VBIOS HDMI retimer register count to array sizeHarry Wentland
[Why & How] The VBIOS integrated info tables (v1_11 and v2_1) contain HdmiRegNum and Hdmi6GRegNum fields that are used as loop bounds when copying retimer I2C register settings into fixed-size arrays (dp*_ext_hdmi_reg_settings[9] and dp*_ext_hdmi_6g_reg_settings[3]). These u8 fields are not validated before use, so a malformed VBIOS can specify values up to 255, causing an out-of-bounds heap write during driver probe. Clamp each register count to the destination array size using min_t() before the copy loops, in both get_integrated_info_v11() and get_integrated_info_v2_1(). Assisted-by: GitHub Copilot:claude-opus-4.6 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Change default driver setting for "Force ODM2:1 for eDP" policyOvidiu Bunea
[Why & How] Change the driver setting: force single eDP ODM2:1 disable as default. Still allow user to enable it via debug option. Revert to unblock testing. Reviewed-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Fix out-of-bounds read in dp_get_eq_aux_rd_interval()Harry Wentland
[Why & How] The aux_rd_interval array in struct dc_lttpr_caps is declared with MAX_REPEATER_CNT - 1 (7) elements, indexed 0..6. However, the offset parameter passed to dp_get_eq_aux_rd_interval() can be as large as MAX_REPEATER_CNT (8) when a sink reports 8 LTTPR repeaters via DPCD. This leads to an out-of-bounds read of aux_rd_interval[7] when offset is 8. Fix this by growing aux_rd_interval to MAX_REPEATER_CNT elements to accommodate the full range of valid repeater counts defined by the DP spec. Assisted-by: GitHub Copilot:Claude claude-4-opus Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Add DC_VALIDATE_MODE_AND_PROGRAMMING condition check for ↵Charlene Liu
force odm2:1 [Why & How] Need to limit force ODM 2:1 to DC_VALIDATE_MODE_AND_PROGRAMMING only, i.e. not block isCofunc check for topology mapping allowed. Reviewed-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Check for sharpening case when calculating max vtaps for scalerSamson Tam
[Why & How] - calc_lb_num_partitions has check when scaler is not enabled to use larger LB in calculations for max vtaps based on viewport being 1:1 - however, scaler is forced on when sharpening is enabled, so need to consider this in check - taps is predetermined in spl_get_optimal_number_of_taps prior to calc_lb_num_partitions. Add check for taps not 1 to handle sharpening case Reviewed-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Samson Tam <Samson.Tam@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Add DRAM table fields to clk_mgr_internalWenjing Liu
[Why] Add GPU-accessible DRAM buffer fields for bulk data transfer from PMFW during clock manager initialization. [How] Add dal_init_table and dal_init_table_addr fields to struct clk_mgr_internal for TABLE_DAL_INIT DRAM transfer. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-03drm/amd/display: Add DCN42 PMO init_for_pstate_supportDmytro Laktyushkin
[Why & How] Add pmo_dcn42_init_for_pstate_support mirroring the DCN4 FAMS2 version, but dropping the meta build for scheduling check that is unnecessary and skipping the cofunctionality check. This solves vrr validation issues in multidisplay configs. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.25.1) at 2026-07-09 01:37:36 +0000