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2025-11-01drm/i915/display: Aux Enable and Display powerwell timeoutsSuraj Kandpal
From XE3P we can now poll if the AUX power is up or down define the timeouts for each respectively. Bspec: 68967 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-25-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Define LT PHY PLL state verify functionSuraj Kandpal
Define function to verify the LT PHY PLL state function and call it in intel_modeset_verify_crtc. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-24-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Define function to readout LT Phy PLL stateSuraj Kandpal
Define a function to readout hw state for LT Phy PLL which can be used in get_config function call. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-23-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Define the LT Phy state compare functionSuraj Kandpal
Define function to compare the state and if mismatch is detected dump both the states. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-22-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Enable/Disable Tx after Non TBT Enable sequenceSuraj Kandpal
We need to enable and disable the Tx for each active lane after the Non-TBT enable sequence is done. Bspec: 74500, 74497, 74701 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-21-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Program LT Phy Voltage SwingSuraj Kandpal
Program LT Phy voltage swing using the Swing tables and plug in the function at encoder->set_signal_level Bspec: 74493 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-20-suraj.kandpal@intel.com
2025-11-01drm/i915/ddi: Define LT Phy Swing tablesSuraj Kandpal
Define and initialize LT Phy Swing tables for DP 1.4, 2.1 and eDp. HDMI TMDS is not needed since LT Phy H/w handles that. Bspec: 74493 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-19-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Hook up LT Phy Enable & Disable sequencesSuraj Kandpal
Hook up the LT Phy enable and disable sequences using encoder-> enable/disable_clock and reusing the TBT enable disable sequence from cx0 PHY since it remains the same. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-18-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Program LT Phy Non-TBT PLL disable sequenceSuraj Kandpal
Program in the steps for Non TBT PLL disable sequence. The whole function can be defined in one shot since most of prequiste functions are already coded in. Bspec: 74492 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-17-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Program the rest of the LT Phy Enable sequenceSuraj Kandpal
Program the rest of the LT Phy Non TBT PLL Enable sequence. This can be done in a single patch since the rest of the prequistie functions are already coded in. Bspec: 74492, 69701 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-16-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Program the rest of the PORT_CLOCK_CTL stepsSuraj Kandpal
Program the rest of the steps with regards to PORT_CLOCK_CTL in Non-TBT PLL enable sequence. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-15-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Program the P2P Transaction flow for LT PhySuraj Kandpal
Program the LT PHY P2P transaction which uses P2M cycle to get get data fro Phy when it is ready and then go read the MAC register from the MAC address space. Bspec: 68966, 74497, 74483, 74500 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-14-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Add function to calculate LT PHY port clockSuraj Kandpal
Create a reverse algorithm which is used to find port clock from the LT PHY state is provided which is used for comparision & verification functions. Bspec: 74667 Signed-off-by: Nemesa Garg <nemesa.garg@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-13-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Enable SSC during port clock programmingSuraj Kandpal
We enable SSC when we program PORT_CLOCK_CTL register. We logically determine if ssc is enabled or not while we calculate our state. Bspec: 74492, 74667 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-12-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Update the ltpll config table value for eDPSuraj Kandpal
When we get the eDP tables we reuse dp tables for some data rates. We need to modify the 3rd config value of this table to 1 instead of 0 since that is the only difference in the dp and edp table for that particular data rate. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-11-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Program the VDR PLL registers for LT PHYSuraj Kandpal
Fetch the tables which need to be used and program it in the specified VDR register space. Everything is done over the respective lanes. Bspec: 68862, 74500 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-10-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Add LT Phy Programming recipe tablesSuraj Kandpal
Add the LT Phy programming recipe tables for eDP, DP & HDMI and a function to use the correct table. Bspec: 74667 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-9-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Read PHY_VDR_0_CONFIG registerSuraj Kandpal
Read PHY_VDR_0_CONFIG to check if there is any change in the register and decide based on that if P2P sequence to change the data rate of LT PHY are required or not. This scenario only happens if the requested mode uses 1.62Gbps with DP mode since LT PHY defaults to this mode if any other mode is requested we need to follow the whole sequence. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-8-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequenceSuraj Kandpal
Add a wrapper on cx0 powerdown change sequence for LT Phy usage, as the sequence remains unchanged when going from SNPS Phy to LT Phy. Bspec: 74495 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-7-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL for LT PhySuraj Kandpal
Program sequence from port clock ctl except for the SSC enablement part which will be taken care of later. Bspec: 74492 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-6-suraj.kandpal@intel.com
2025-11-01drm/i915/cx0: Move the HDMI FRL function to intel_hdmiSuraj Kandpal
Move the is_hdmi_frl to intel_hdmi.c. Rename it appropriately and make it non static. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-5-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Phy lane reset for LT PhySuraj Kandpal
Define function to bring phy lane out of reset for LT Phy and the corresponding pre-requisite steps before we follow the steps for Phy lane reset. Also create a skeleton of LT PHY PLL enable sequence function in which we can place this function Bspec: 77449, 74749, 74499, 74495, 68960 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-4-suraj.kandpal@intel.com
2025-11-01drm/i915/cx0: Change register bit naming for powerdown valuesSuraj Kandpal
Change the register bit naming for powerdown values from CX0 to XELPDP so that it can be used with LT Phy too. Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-3-suraj.kandpal@intel.com
2025-11-01drm/i915/ltphy: Add LT Phy related VDR and Pipe RegistersSuraj Kandpal
Add LT Phy related VDR and pipe registers into its own new file. Bspec: 74500 Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://patch.msgid.link/20251101032513.4171255-2-suraj.kandpal@intel.com
2025-10-31dpll: zl3073x: Specify phase adjustment granularity for pinsIvan Vecera
Output pins phase adjustment values in the device are expressed in half synth clock cycles. Use this number of cycles as output pins' phase adjust granularity and simplify both get/set callbacks. Reviewed-by: Michal Schmidt <mschmidt@redhat.com> Reviewed-by: Petr Oros <poros@redhat.com> Tested-by: Prathosh Satish <Prathosh.Satish@microchip.com> Signed-off-by: Ivan Vecera <ivecera@redhat.com> Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> Link: https://patch.msgid.link/20251029153207.178448-3-ivecera@redhat.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-10-31dpll: add phase-adjust-gran pin attributeIvan Vecera
Phase-adjust values are currently limited by a min-max range. Some hardware requires, for certain pin types, that values be multiples of a specific granularity, as in the zl3073x driver. Add a `phase-adjust-gran` pin attribute and an appropriate field in dpll_pin_properties. If set by the driver, use its value to validate user-provided phase-adjust values. Reviewed-by: Michal Schmidt <mschmidt@redhat.com> Reviewed-by: Petr Oros <poros@redhat.com> Tested-by: Prathosh Satish <Prathosh.Satish@microchip.com> Signed-off-by: Ivan Vecera <ivecera@redhat.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> Link: https://patch.msgid.link/20251029153207.178448-2-ivecera@redhat.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-10-31net: pse-pd: tps23881: Add support for TPS23881BThomas Wismer
The TPS23881B uses different firmware than the TPS23881. Trying to load the TPS23881 firmware on a TPS23881B device fails and must be omitted. The TPS23881B ships with a more recent ROM firmware. Moreover, no updated firmware has been released yet and so the firmware loading step must be skipped. As of today, the TPS23881B is intended to use its ROM firmware. Signed-off-by: Thomas Wismer <thomas.wismer@scs.ch> Reviewed-by: Kory Maincent <kory.maincent@bootlin.com> Acked-by: Oleksij Rempel <o.rempel@pengutronix.de> Link: https://patch.msgid.link/20251029212312.108749-2-thomas@wismer.xyz Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-10-31netconsole: Acquire su_mutex before navigating configs hierarchyGustavo Luiz Duarte
There is a race between operations that iterate over the userdata cg_children list and concurrent add/remove of userdata items through configfs. The update_userdata() function iterates over the nt->userdata_group.cg_children list, and count_extradata_entries() also iterates over this same list to count nodes. Quoting from Documentation/filesystems/configfs.rst: > A subsystem can navigate the cg_children list and the ci_parent pointer > to see the tree created by the subsystem. This can race with configfs' > management of the hierarchy, so configfs uses the subsystem mutex to > protect modifications. Whenever a subsystem wants to navigate the > hierarchy, it must do so under the protection of the subsystem > mutex. Without proper locking, if a userdata item is added or removed concurrently while these functions are iterating, the list can be accessed in an inconsistent state. For example, the list_for_each() loop can reach a node that is being removed from the list by list_del_init() which sets the nodes' .next pointer to point to itself, so the loop will never end (or reach the WARN_ON_ONCE in update_userdata() ). Fix this by holding the configfs subsystem mutex (su_mutex) during all operations that iterate over cg_children. This includes: - userdatum_value_store() which calls update_userdata() to iterate over cg_children - All sysdata_*_enabled_store() functions which call count_extradata_entries() to iterate over cg_children The su_mutex must be acquired before dynamic_netconsole_mutex to avoid potential lock ordering issues, as configfs operations may already hold su_mutex when calling into our code. Fixes: df03f830d099 ("net: netconsole: cache userdata formatted string in netconsole_target") Signed-off-by: Gustavo Luiz Duarte <gustavold@gmail.com> Link: https://patch.msgid.link/20251029-netconsole-fix-warn-v1-1-0d0dd4622f48@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-10-31isdn: mISDN: hfcsusb: fix memory leak in hfcsusb_probe()Abdun Nihaal
In hfcsusb_probe(), the memory allocated for ctrl_urb gets leaked when setup_instance() fails with an error code. Fix that by freeing the urb before freeing the hw structure. Also change the error paths to use the goto ladder style. Compile tested only. Issue found using a prototype static analysis tool. Fixes: 69f52adb2d53 ("mISDN: Add HFC USB driver") Signed-off-by: Abdun Nihaal <nihaal@cse.iitm.ac.in> Link: https://patch.msgid.link/20251030042524.194812-1-nihaal@cse.iitm.ac.in Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-10-31net: phy: microchip_t1s: configure link status control for LAN867x Rev.D0Parthiban Veerasooran
Configure the link status in the Link Status Control register for LAN8670/1/2 Rev.D0 PHYs, depending on whether PLCA or CSMA/CD mode is enabled. When PLCA is enabled, the link status reflects the PLCA status. When PLCA is disabled (CSMA/CD mode), the PHY does not support autonegotiation, so the link status is forced active by setting the LINK_STATUS_SEMAPHORE bit. The link status control is configured: - During PHY initialization, for default CSMA/CD mode. - Whenever PLCA configuration is updated. This ensures correct link reporting and consistent behavior for LAN867x Rev.D0 devices. Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/20251030102258.180061-3-parthiban.veerasooran@microchip.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-10-31net: phy: microchip_t1s: add support for Microchip LAN867X Rev.D0 PHYParthiban Veerasooran
Add support for the LAN8670/1/2 Rev.D0 10BASE-T1S PHYs from Microchip. The new Rev.D0 silicon requires a specific set of initialization settings to be configured for optimal performance and compliance with OPEN Alliance specifications, as described in Microchip Application Note AN1699 (Revision G, DS60001699G – October 2025). https://www.microchip.com/en-us/application-notes/an1699 Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/20251030102258.180061-2-parthiban.veerasooran@microchip.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-10-31net: stmmac: qcom-ethqos: remove MAC_CTRL_REG modificationRussell King (Oracle)
When operating in "SGMII" mode (Cisco SGMII or 2500BASE-X), qcom-ethqos modifies the MAC control register in its ethqos_configure_sgmii() function, which is only called from one path: stmmac_mac_link_up() +- reads MAC_CTRL_REG +- masks out priv->hw->link.speed_mask +- sets bits according to speed (2500, 1000, 100, 10) from priv->hw.link.speed* +- ethqos_fix_mac_speed() | +- qcom_ethqos_set_sgmii_loopback(false) | +- ethqos_update_link_clk(speed) | `- ethqos_configure(speed) | `- ethqos_configure_sgmii(speed) | +- reads MAC_CTRL_REG, | +- configures PS/FES bits according to speed | `- writes MAC_CTRL_REG as the last operation +- sets duplex bit(s) +- stmmac_mac_flow_ctrl() +- writes MAC_CTRL_REG if changed from original read ... As can be seen, the modification of the control register that stmmac_mac_link_up() overwrites the changes that ethqos_fix_mac_speed() does to the register. This makes ethqos_configure_sgmii()'s modification questionable at best. Analysing the values written, GMAC4 sets the speed bits as: speed_mask = GMAC_CONFIG_FES | GMAC_CONFIG_PS speed2500 = GMAC_CONFIG_FES B14=1 B15=0 speed1000 = 0 B14=0 B15=0 speed100 = GMAC_CONFIG_FES | GMAC_CONFIG_PS B14=1 B15=1 speed10 = GMAC_CONFIG_PS B14=0 B15=1 Whereas ethqos_configure_sgmii(): 2500: clears ETHQOS_MAC_CTRL_PORT_SEL B14=X B15=0 1000: clears ETHQOS_MAC_CTRL_PORT_SEL B14=X B15=0 100: sets ETHQOS_MAC_CTRL_PORT_SEL | B14=1 B15=1 ETHQOS_MAC_CTRL_SPEED_MODE 10: sets ETHQOS_MAC_CTRL_PORT_SEL B14=0 B15=1 clears ETHQOS_MAC_CTRL_SPEED_MODE Thus, they appear to be doing very similar, with the exception of the FES bit (bit 14) for 1G and 2.5G speeds. Given that stmmac_mac_link_up() will write the MAC_CTRL_REG after ethqos_configure_sgmii(), remove the unnecessary update in the glue driver's ethqos_configure_sgmii() method, simplifying the code. Konrad states: Without any additional knowledge, the register description says: 2500: B14=1 B15=0 1000: B14=0 B15=0 100: B14=1 B15=1 10: B14=0 B15=1 Tested-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://patch.msgid.link/E1vEPlg-0000000CFHY-282A@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-10-31net/mlx5e: Convert to new hwtstamp_get/set interfaceCarolina Jubran
Migrate from the legacy ioctl hardware timestamping interface to the ndo_hwtstamp_get/set operations. Signed-off-by: Carolina Jubran <cjubran@nvidia.com> Reviewed-by: Cosmin Ratiu <cratiu@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Link: https://patch.msgid.link/1761819910-1011051-7-git-send-email-tariqt@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-10-31IB/IPoIB: Add support for hwtstamp get/set ndosCarolina Jubran
Add support for the ndo_hwtstamp_get and ndo_hwtstamp_set operations in IPoIB. This allows lower devices to handle hardware timestamp configuration through the new ndos instead of the legacy ioctls. Signed-off-by: Carolina Jubran <cjubran@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Link: https://patch.msgid.link/1761819910-1011051-6-git-send-email-tariqt@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-10-31net/mlx5e: Rename timestamp fields to hwtstamp_configCarolina Jubran
Rename hardware timestamp-related fields from 'tstamp' to 'hwtstamp_config' throughout the MLX5 driver. The new name is more descriptive as it clearly indicates these fields contain hardware timestamp configuration. Signed-off-by: Carolina Jubran <cjubran@nvidia.com> Reviewed-by: Cosmin Ratiu <cratiu@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Link: https://patch.msgid.link/1761819910-1011051-5-git-send-email-tariqt@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-10-31net/mlx5e: Rename hwstamp functions to hwtstampCarolina Jubran
Rename mlx5e_hwstamp_set/get() functions to mlx5e_hwtstamp_set/get() to better reflect that these functions handle hardware timestamping, not just hardware stamping. Signed-off-by: Carolina Jubran <cjubran@nvidia.com> Reviewed-by: Cosmin Ratiu <cratiu@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Link: https://patch.msgid.link/1761819910-1011051-4-git-send-email-tariqt@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-10-31net/mlx5e: Remove unnecessary tstamp local variable in mlx5i_complete_rx_cqeCarolina Jubran
Remove the tstamp local variable in mlx5i_complete_rx_cqe() and directly pass the tstamp field from priv to mlx5e_rx_hw_stamp(). The local variable was only used once and provided no additional value. Signed-off-by: Carolina Jubran <cjubran@nvidia.com> Reviewed-by: Cosmin Ratiu <cratiu@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Link: https://patch.msgid.link/1761819910-1011051-3-git-send-email-tariqt@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-10-31net/mlx5e: Remove redundant tstamp pointer from channel structuresCarolina Jubran
Remove the tstamp pointer field from mlx5e_channel, mlx5e_ptp, and mlx5e_trap structures, since it was only used to reference the tstamp field in the priv structure. Instead, directly use the tstamp field from priv when initializing RQ structures. Also remove the unused hwtstamp_config field from mlx5_clock structure as part of the cleanup. Signed-off-by: Carolina Jubran <cjubran@nvidia.com> Reviewed-by: Cosmin Ratiu <cratiu@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Link: https://patch.msgid.link/1761819910-1011051-2-git-send-email-tariqt@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-10-31ptp: Allow exposing cycles only for clocks with free-running counterCarolina Jubran
The PTP core falls back to gettimex64 and getcrosststamp when getcycles64 or getcyclesx64 are not implemented. This causes the CYCLES ioctls to retrieve PHC real time instead of free-running cycles. Reject PTP_SYS_OFFSET_{PRECISE,EXTENDED}_CYCLES for clocks without free-running counter support since the result would represent PHC real time and system time rather than cycles and system time. Fixes: faf23f54d366 ("ptp: Add ioctl commands to expose raw cycle counter values") Signed-off-by: Carolina Jubran <cjubran@nvidia.com> Reviewed-by: Dragos Tatulea <dtatulea@nvidia.com> Reviewed-by: Tariq Toukan <tariqt@nvidia.com> Reviewed-by: Pavan Chebbi <pavan.chebbi@broadcom.com> Reviewed-by: Vadim Fedorenko <vadim.fedorenko@linux.dev> Link: https://patch.msgid.link/20251029083813.2276997-1-cjubran@nvidia.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-10-31net: mana: Support HW link state eventsHaiyang Zhang
Handle the NIC hardware link state events received from the HW channel, then set the proper link state accordingly. And, add a feature bit, GDMA_DRV_CAP_FLAG_1_HW_VPORT_LINK_AWARE, to inform the NIC hardware this handler exists. Our MANA NIC only sends out the link state down/up messages when we need to let the VM rerun DHCP client and change IP address. So, add netif_carrier_on() in the probe(), let the NIC show the right initial state in /sys/class/net/ethX/operstate. Signed-off-by: Haiyang Zhang <haiyangz@microsoft.com> Link: https://patch.msgid.link/1761770601-16920-1-git-send-email-haiyangz@linux.microsoft.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-10-31gve: Implement settime64 with -EOPNOTSUPPTim Hostetler
ptp_clock_settime() assumes every ptp_clock has implemented settime64(). Stub it with -EOPNOTSUPP to prevent a NULL dereference. Fixes: acd16380523b ("gve: Add initial PTP device support") Reported-by: syzbot+a546141ca6d53b90aba3@syzkaller.appspotmail.com Closes: https://syzkaller.appspot.com/bug?extid=a546141ca6d53b90aba3 Signed-off-by: Tim Hostetler <thostet@google.com> Reviewed-by: Kuniyuki Iwashima <kuniyu@google.com> Signed-off-by: Joshua Washington <joshwash@google.com> Link: https://patch.msgid.link/20251029184555.3852952-3-joshwash@google.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-10-31gve: Implement gettimex64 with -EOPNOTSUPPTim Hostetler
gve implemented a ptp_clock for sole use of do_aux_work at this time. ptp_clock_gettime() and ptp_sys_offset() assume every ptp_clock has implemented either gettimex64 or gettime64. Stub gettimex64 and return -EOPNOTSUPP to prevent NULL dereferencing. Fixes: acd16380523b ("gve: Add initial PTP device support") Reported-by: syzbot+c8c0e7ccabd456541612@syzkaller.appspotmail.com Closes: https://syzkaller.appspot.com/bug?extid=c8c0e7ccabd456541612 Signed-off-by: Tim Hostetler <thostet@google.com> Reviewed-by: Harshitha Ramamurthy <hramamurthy@google.com> Reviewed-by: Kuniyuki Iwashima <kuniyu@google.com> Signed-off-by: Joshua Washington <joshwash@google.com> Link: https://patch.msgid.link/20251029184555.3852952-2-joshwash@google.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-10-31Merge tag 'drm-fixes-2025-10-31' of https://gitlab.freedesktop.org/drm/kernelLinus Torvalds
Pull drm fixes from Simona Vetter: "Looks like stochastics conspired to make this one a bit bigger, but nothing scary at all. Also first examples of the new Link: tags, yay! Next week Dave should be back. Drivers: - mediatek: uaf in unbind, fixes -rc2 boot regression - radeon: devm conversion fixes - amdgpu: VPE idle handler, re-enable DM idle optimization, DCN3, SMU, vblank, HDP eDP, powerplay fixes for fiji/iceland - msm: bunch of gem error path fixes, gmu fw parsing fix, dpu fixes - intel: fix dmc/dc6 asserts on ADL-S - xe: fix xe_validation_guard(), wake device handling around gt reset - ast: fix display output on AST2300 - etnaviv: fix gpu flush - imx: fix parallel bridge handling - nouveau: scheduler locking fix - panel: fixes for kingdisplay-kd097d04 and sitronix-st7789v Core Changes: - CI: disable broken sanity job - sysfb: fix NULL pointer access - sched: fix SIGKILL handling, locking for race condition - dma_fence: better timeline name for signalled fences" * tag 'drm-fixes-2025-10-31' of https://gitlab.freedesktop.org/drm/kernel: (44 commits) drm/ast: Clear preserved bits from register output value drm/imx: parallel-display: add the bridge before attaching it drm/imx: parallel-display: convert to devm_drm_bridge_alloc() API drm/panel: kingdisplay-kd097d04: Disable EoTp drm/panel: sitronix-st7789v: fix sync flags for t28cp45tn89 drm/xe: Do not wake device during a GT reset drm/xe: Fix uninitialized return value from xe_validation_guard() drm/msm/dpu: Fix adjusted mode clock check for 3d merge drm/msm/dpu: Disable broken YUV on QSEED2 hardware drm/msm/dpu: Require linear modifier for writeback framebuffers drm/msm/dpu: Fix pixel extension sub-sampling drm/msm/dpu: Disable scaling for unsupported scaler types drm/msm/dpu: Propagate error from dpu_assign_plane_resources drm/msm/dpu: Fix allocation of RGB SSPPs without scaling drm/msm: dsi: fix PLL init in bonded mode drm/i915/dmc: Clear HRR EVT_CTL/HTP to zero on ADL-S drm/amd/display: Fix incorrect return of vblank enable on unconfigured crtc drm/amd/display: Add HDR workaround for a specific eDP drm/amdgpu: fix SPDX header on cyan_skillfish_reg_init.c drm/amdgpu: fix SPDX header on irqsrcs_vcn_5_0.h ...
2025-10-31Merge tag 'pci-v6.18-fixes-4' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci Pull pci fixes from Bjorn Helgaas: - Restore custom qcom ASPM enablement code so L1 PM Substates are enabled as they were in v6.17 even though the PCI core now enables just L0s and L1 by default (Bjorn Helgaas) - Size prefetchable bridge windows only when they actually exist, to avoid a WARN_ON() regression (Ilpo Järvinen) * tag 'pci-v6.18-fixes-4' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: PCI: Do not size non-existing prefetchable window Revert "PCI: qcom: Remove custom ASPM enablement code"
2025-10-31PCI: qcom: Use frequency and level based OPP lookupKrishna Chaitanya Chundru
PCIe link configurations such as 8GT/s x2 and 16GT/s x1 may operate at the same frequency, but differ in other characteristics like RPMh votes. But the existing OPP selection which is solely based on frequency (the 'opp-hz' DT property) cannot distinguish between such cases. Hence, use the newly introduced dev_pm_opp_find_key_exact() API to match both frequency and level (the 'opp-level' property) when selecting an OPP, here level indicates PCIe data rate. To support older device trees where opp-level is not defined, check if opp-level is present or not using dev_pm_opp_find_level_exact(). If not present fallback to frequency only match. Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com> [mani: zero initialize dev_pm_opp_key struct] Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> [bhelgaas: add 'opp-hz' and 'opp-level' in commit log] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20251013-opp_pcie-v5-5-eb64db2b4bd3@oss.qualcomm.com
2025-10-31Merge tag 'vfio-v6.18-rc4' of https://github.com/awilliam/linux-vfioLinus Torvalds
Pull VFIO fixes from Alex Williamson: - Fix overflows in vfio type1 backend for mappings at the end of the 64-bit address space, resulting in leaked pinned memory. New selftest support included to avoid such issues in the future (Alex Mastro) * tag 'vfio-v6.18-rc4' of https://github.com/awilliam/linux-vfio: vfio: selftests: add end of address space DMA map/unmap tests vfio: selftests: update DMA map/unmap helpers to support more test kinds vfio/type1: handle DMA map/unmap up to the addressable limit vfio/type1: move iova increment to unmap_unpin_*() caller vfio/type1: sanitize for overflow using check_*_overflow()
2025-10-31Merge tag 'amd-drm-next-6.19-2025-10-29' of ↵Simona Vetter
https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-6.19-2025-10-29: amdgpu: - VPE idle handler fix - Re-enable DM idle optimizations - DCN3.0 fix - SMU fix - Powerplay fixes for fiji/iceland - License copy-pasta fixes - HDP eDP panel fix - Vblank fix - RAS fixes - SR-IOV updates - SMU 13 VCN reset fix - DMUB fixes - DC frame limit fix - Additional DC underflow logging - DCN 3.1.5 fixes - DC Analog encoders support - Enable DC on bonaire by default - UserQ fixes - Remove redundant pm_runtime_mark_last_busy() calls amdkfd: - Process cleanup fix - Misc fixes radeon: - devm migration fixes - Remove redundant pm_runtime_mark_last_busy() calls UAPI - Add ABM KMS property Proposed kwin changes: https://invent.kde.org/plasma/kwin/-/merge_requests/6028 Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patch.msgid.link/20251029205713.9480-1-alexander.deucher@amd.com
2025-10-31PCI: Do not size non-existing prefetchable windowIlpo Järvinen
pbus_size_mem() should only be called for bridge windows that exist but __pci_bus_size_bridges() may point 'pref' to a resource that does not exist (has zero flags) in case of non-root buses. When prefetchable bridge window does not exist, the same non-prefetchable bridge window is sized more than once which may result in duplicating entries into the realloc_head list. Duplicated entries are shown in this log and trigger a WARN_ON() because realloc_head had residual entries after the resource assignment algorithm: pci 0000:00:03.0: [11ab:6820] type 01 class 0x060400 PCIe Root Port pci 0000:00:03.0: PCI bridge to [bus 00] pci 0000:00:03.0: bridge window [io 0x0000-0x0fff] pci 0000:00:03.0: bridge window [mem 0x00000000-0x000fffff] pci 0000:00:03.0: bridge window [mem 0x00200000-0x003fffff] to [bus 02] add_size 200000 add_align 200000 pci 0000:00:03.0: bridge window [mem 0x00200000-0x003fffff] to [bus 02] add_size 200000 add_align 200000 pci 0000:00:03.0: bridge window [mem 0xe0000000-0xe03fffff]: assigned pci 0000:00:03.0: PCI bridge to [bus 02] pci 0000:00:03.0: bridge window [mem 0xe0000000-0xe03fffff] ------------[ cut here ]------------ WARNING: CPU: 0 PID: 1 at drivers/pci/setup-bus.c:2373 pci_assign_unassigned_root_bus_resources+0x1bc/0x234 Check resource flags of 'pref' and only size the prefetchable window if the resource has the IORESOURCE_PREFETCH flag. Fixes: ae88d0b9c57f ("PCI: Use pbus_select_window_for_type() during mem window sizing") Reported-by: Klaus Kudielka <klaus.kudielka@gmail.com> Closes: https://lore.kernel.org/r/51e8cf1c62b8318882257d6b5a9de7fdaaecc343.camel@gmail.com/ Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Klaus Kudielka <klaus.kudielka@gmail.com> Link: https://patch.msgid.link/20251027132423.8841-1-ilpo.jarvinen@linux.intel.com
2025-10-31Revert "PCI: qcom: Remove custom ASPM enablement code"Bjorn Helgaas
This reverts commit a729c16646198872e345bf6c48dbe540ad8a9753. Prior to a729c1664619 ("PCI: qcom: Remove custom ASPM enablement code"), the qcom controller driver enabled ASPM, including L0s, L1, and L1 PM Substates, for all devices powered on at the time the controller driver enumerates them. ASPM was *not* enabled for devices powered on later by pwrctrl (unless the kernel was built with PCIEASPM_POWERSAVE or PCIEASPM_POWER_SUPERSAVE, or the user enabled ASPM via module parameter or sysfs). After f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for devicetree platforms"), the PCI core enabled all ASPM states for all devices whether powered on initially or by pwrctrl, so a729c1664619 was unnecessary and reverted. But f3ac2ff14834 was too aggressive and broke platforms that didn't support CLKREQ# or required device-specific configuration for L1 Substates, so df5192d9bb0e ("PCI/ASPM: Enable only L0s and L1 for devicetree platforms") enabled only L0s and L1. On Qualcomm platforms, this left L1 Substates disabled, which was a regression. Revert a729c1664619 so L1 Substates will be enabled on devices that are initially powered on. Devices powered on by pwrctrl will be addressed later. Fixes: df5192d9bb0e ("PCI/ASPM: Enable only L0s and L1 for devicetree platforms") Reported-by: Johan Hovold <johan@kernel.org> Closes: https://lore.kernel.org/lkml/aPuXZlaawFmmsLmX@hovoldconsulting.com/ Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Tested-by: Johan Hovold <johan@kernel.org> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org> Link: https://patch.msgid.link/20251024210514.1365996-1-helgaas@kernel.org
2025-10-31Merge tag 'block-6.18-20251031' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux Pull block fixes from Jens Axboe: - Fix blk-crypto reporting EIO when EINVAL is the correct error code - Two bug fixes for the block zone support - NVME pull request via Keith: - Target side authentication fixup - Peer-to-peer metadata fixup - null_blk DMA alignment fix * tag 'block-6.18-20251031' of git://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux: null_blk: set dma alignment to logical block size blk-crypto: use BLK_STS_INVAL for alignment errors block: make REQ_OP_ZONE_OPEN a write operation block: fix op_is_zone_mgmt() to handle REQ_OP_ZONE_RESET_ALL nvme-pci: use blk_map_iter for p2p metadata nvmet-auth: update sc_c in host response
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-23 06:16:03 +0000